1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <drivers/arm/gic600_multichip.h> 9 #include <plat/arm/common/plat_arm.h> 10 #include <plat/common/platform.h> 11 #include <sgi_soc_platform_def.h> 12 #include <sgi_plat.h> 13 14 #if defined(IMAGE_BL31) 15 static const mmap_region_t rdv1mc_dynamic_mmap[] = { 16 ARM_MAP_SHARED_RAM_REMOTE_CHIP(1), 17 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1), 18 SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1), 19 #if (CSS_SGI_CHIP_COUNT > 2) 20 ARM_MAP_SHARED_RAM_REMOTE_CHIP(2), 21 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2), 22 SOC_CSS_MAP_DEVICE_REMOTE_CHIP(2), 23 #endif 24 #if (CSS_SGI_CHIP_COUNT > 3) 25 ARM_MAP_SHARED_RAM_REMOTE_CHIP(3), 26 CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3), 27 SOC_CSS_MAP_DEVICE_REMOTE_CHIP(3) 28 #endif 29 }; 30 31 static struct gic600_multichip_data rdv1mc_multichip_data __init = { 32 .rt_owner_base = PLAT_ARM_GICD_BASE, 33 .rt_owner = 0, 34 .chip_count = CSS_SGI_CHIP_COUNT, 35 .chip_addrs = { 36 PLAT_ARM_GICD_BASE >> 16, 37 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16, 38 #if (CSS_SGI_CHIP_COUNT > 2) 39 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16, 40 #endif 41 #if (CSS_SGI_CHIP_COUNT > 3) 42 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16, 43 #endif 44 }, 45 .spi_ids = { 46 {PLAT_ARM_GICD_BASE, 32, 255}, 47 {0, 0, 0}, 48 #if (CSS_SGI_CHIP_COUNT > 2) 49 {0, 0, 0}, 50 #endif 51 #if (CSS_SGI_CHIP_COUNT > 3) 52 {0, 0, 0}, 53 #endif 54 } 55 }; 56 57 static uintptr_t rdv1mc_multichip_gicr_frames[] = { 58 /* Chip 0's GICR Base */ 59 PLAT_ARM_GICR_BASE, 60 /* Chip 1's GICR BASE */ 61 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1), 62 #if (CSS_SGI_CHIP_COUNT > 2) 63 /* Chip 2's GICR BASE */ 64 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2), 65 #endif 66 #if (CSS_SGI_CHIP_COUNT > 3) 67 /* Chip 3's GICR BASE */ 68 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3), 69 #endif 70 UL(0) /* Zero Termination */ 71 }; 72 #endif /* IMAGE_BL31 */ 73 74 unsigned int plat_arm_sgi_get_platform_id(void) 75 { 76 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) 77 & SID_SYSTEM_ID_PART_NUM_MASK; 78 } 79 80 unsigned int plat_arm_sgi_get_config_id(void) 81 { 82 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET); 83 } 84 85 unsigned int plat_arm_sgi_get_multi_chip_mode(void) 86 { 87 return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) & 88 SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT; 89 } 90 91 /* 92 * bl31_platform_setup_function is guarded by IMAGE_BL31 macro because 93 * PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not 94 * for other stages. 95 */ 96 #if defined(IMAGE_BL31) 97 void bl31_platform_setup(void) 98 { 99 int ret; 100 unsigned int i; 101 102 if ((plat_arm_sgi_get_multi_chip_mode() == 0) && 103 (CSS_SGI_CHIP_COUNT > 1)) { 104 ERROR("Chip Count is set to %u but multi-chip mode is not " 105 "enabled\n", CSS_SGI_CHIP_COUNT); 106 panic(); 107 } else if ((plat_arm_sgi_get_multi_chip_mode() == 1) && 108 (CSS_SGI_CHIP_COUNT > 1)) { 109 INFO("Enabling support for multi-chip in RD-V1-MC\n"); 110 111 for (i = 0; i < ARRAY_SIZE(rdv1mc_dynamic_mmap); i++) { 112 ret = mmap_add_dynamic_region( 113 rdv1mc_dynamic_mmap[i].base_pa, 114 rdv1mc_dynamic_mmap[i].base_va, 115 rdv1mc_dynamic_mmap[i].size, 116 rdv1mc_dynamic_mmap[i].attr); 117 if (ret != 0) { 118 ERROR("Failed to add dynamic mmap entry " 119 "(ret=%d)\n", ret); 120 panic(); 121 } 122 } 123 124 plat_arm_override_gicr_frames( 125 rdv1mc_multichip_gicr_frames); 126 gic600_multichip_init(&rdv1mc_multichip_data); 127 } 128 129 sgi_bl31_common_platform_setup(); 130 } 131 #endif /* IMAGE_BL31 */ 132