1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (C) 2024, Charleye <wangkart@aliyun.com> 4 * All rights reserved. 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 #include <lua_def.h> 11 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/ti/uart/uart_16550.h> 18 #include <lib/mmio.h> 19 #include <plat/common/platform.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <lib/extensions/ras.h> 22 23 static entry_point_info_t bl32_image_ep_info; 24 static entry_point_info_t bl33_image_ep_info; 25 26 /* 27 * Table of regions to map using the MMU. 28 * This doesn't include TZRAM as the 'mem_layout' argument passed to 29 * configure_mmu_elx() will give the available subset of that, 30 */ 31 const mmap_region_t plat_lua_mmap[] = { 32 MAP_REGION_FLAT(DEVICE_BASE, DEVICE_SIZE, MT_DEVICE | MT_RW | MT_NS), 33 MAP_REGION_FLAT(GICD_BASE, GICD_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 34 MAP_REGION_FLAT(CPU_SYSCTL_BASE, CPU_SYSCTL_SIZE, MT_DEVICE | MT_RW | MT_NS), 35 PLAT_LUA_BOOT_MMAP, 36 { 0 } 37 }; 38 39 const mmap_region_t *plat_lua_get_mmap(void) 40 { 41 return plat_lua_mmap; 42 } 43 44 unsigned int plat_get_syscnt_freq2(void) 45 { 46 return LUA_OSC24M_CLK_IN_HZ; 47 } 48 49 /******************************************************************************* 50 * Return a pointer to the 'entry_point_info' structure of the next image for 51 * the security state specified. BL33 corresponds to the non-secure image type 52 * while BL32 corresponds to the secure image type. A NULL pointer is returned 53 * if the image does not exist. 54 ******************************************************************************/ 55 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 56 { 57 entry_point_info_t *next_image_info; 58 59 //assert(sec_state_is_valid(type)); 60 next_image_info = (type == NON_SECURE) ? \ 61 &bl33_image_ep_info : &bl32_image_ep_info; 62 63 /* None of the images on this platform can have 0x0 as the entrypoint */ 64 if (next_image_info->pc) 65 return next_image_info; 66 else 67 return NULL; 68 } 69 70 /* 71 * Set the build time defaults,if we can't find any config data. 72 */ 73 static inline void bl31_set_default_config(void) 74 { 75 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 76 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry(); 77 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint(); 78 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 79 } 80 81 static void lua_print_platform_name(void) 82 { 83 NOTICE("ATF running on %s\n", PLATFORM_NAME); 84 } 85 86 void lua_config_setup(void) 87 { 88 lua_print_platform_name(); 89 90 generic_delay_timer_init(); 91 } 92 93 /******************************************************************************* 94 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 95 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 96 * are lost (potentially). This needs to be done before the MMU is initialized 97 * so that the memory layout can be used while creating page tables. 98 * BL2 has flushed this information to memory, so we are guaranteed to pick up 99 * good data. 100 ******************************************************************************/ 101 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 102 u_register_t arg2, u_register_t arg3) 103 { 104 lua_console_init(); 105 106 /* Initialize the platform config for future decision making */ 107 lua_config_setup(); 108 109 /* 110 * Do initial security configuration to allow DRAM/device access. On 111 * Base Sigi only DRAM security is programmable (via TrustZone), but 112 * other platforms might have more programmable security devices 113 * present. 114 */ 115 116 /* Populate common information for BL32 and BL33 */ 117 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 118 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 119 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 120 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 121 122 bl31_set_default_config(); 123 124 VERBOSE("BL31: early platform setup\n"); 125 NOTICE("BL31: Secure code at 0x%08lx\n", bl32_image_ep_info.pc); 126 NOTICE("BL31: Non secure code at 0x%08lx\n", bl33_image_ep_info.pc); 127 } 128 129 #ifdef LUA_SEC_UART1_IRQ 130 static int uart1_interrupt_handler(uint32_t intr_raw, uint32_t flags, 131 void *handle, void *cookie) 132 { 133 NOTICE("An UART1 interrupt is taken from non-secure EL1/EL2 to EL3.\n"); 134 135 /* Disable all interrupts */ 136 mmio_write_32(PLAT_LUA_UART1_BASE + UARTIER, 0x0); 137 138 plat_ic_end_of_interrupt(intr_raw); 139 140 return 0; 141 } 142 #endif 143 144 #define PERIPH_GLB_BASE U(0x0E000000) 145 static int fab_periph_interrupt_handler(uint32_t intr_raw, uint32_t flags, 146 void *handle, void *cookie) 147 { 148 NOTICE("An fab_periph (%d) interrupt is taken from non-secure EL1/EL2 to EL3.\n", intr_raw); 149 150 uint32_t fab_periph_irq = mmio_read_32(PERIPH_GLB_BASE + 0x24); 151 INFO("fab_periph_irq status = %x\n", fab_periph_irq); 152 153 /* Clear fab_periph interrupt */ 154 mmio_write_32(PERIPH_GLB_BASE + 0x14, BIT(0)); 155 mmio_write_32(PERIPH_GLB_BASE + 0x20, BIT(0)); 156 157 plat_ic_end_of_interrupt(intr_raw); 158 159 return 0; 160 } 161 162 /******************************************************************************* 163 * Perform any BL3-1 platform setup code 164 ******************************************************************************/ 165 void bl31_platform_setup(void) 166 { 167 /* Initialize the gic cpu and distributor interfaces */ 168 plat_lua_gic_init(); 169 170 #ifdef LUA_SEC_UART1_IRQ 171 ehf_register_priority_handler(PLAT_LUA_UART1_PRIO, 172 uart1_interrupt_handler); 173 #endif 174 175 ehf_register_priority_handler(PLAT_LUA_FAB_PERIPH_PRIO, 176 fab_periph_interrupt_handler); 177 178 #if ENABLE_FEAT_RAS && FFH_SUPPORT 179 ras_init(); 180 #endif 181 } 182 183 /******************************************************************************* 184 * Perform the very early platform specific architectural setup here. At the 185 * moment this is only intializes the mmu in a quick and dirty way. 186 ******************************************************************************/ 187 void bl31_plat_arch_setup(void) 188 { 189 const mmap_region_t bl_regions[] = { 190 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 191 MT_MEMORY | MT_RW | MT_SECURE), 192 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 193 MT_CODE | MT_SECURE), 194 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA| MT_SECURE), 195 MAP_REGION_FLAT(SHARED_RAM_BASE, SHARED_RAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE), 196 {0} 197 }; 198 setup_page_tables(bl_regions, plat_lua_get_mmap()); 199 enable_mmu_el3(0); 200 } 201