1 /* 2 * Copyright (c) 2016-2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 15 #include <platform_def.h> 16 17 static void brcm_stingray_pnor_pinmux_init(void) 18 { 19 unsigned int i; 20 21 INFO(" - pnor pinmux init start.\n"); 22 23 /* Set PNOR_ADV_N_MODE_SEL_CONTROL.fsel = 0x2 */ 24 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2dc), 25 MODE_SEL_CONTROL_FSEL_MASK, 26 MODE_SEL_CONTROL_FSEL_MODE2); 27 28 /* Set PNOR_BAA_N_MODE_SEL_CONTROL.fsel = 0x2 */ 29 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e0), 30 MODE_SEL_CONTROL_FSEL_MASK, 31 MODE_SEL_CONTROL_FSEL_MODE2); 32 33 /* Set PNOR_BLS_0_N_MODE_SEL_CONTROL.fsel = 0x2 */ 34 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e4), 35 MODE_SEL_CONTROL_FSEL_MASK, 36 MODE_SEL_CONTROL_FSEL_MODE2); 37 38 /* Set PNOR_BLS_1_N_MODE_SEL_CONTROL.fsel = 0x2 */ 39 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e8), 40 MODE_SEL_CONTROL_FSEL_MASK, 41 MODE_SEL_CONTROL_FSEL_MODE2); 42 43 /* Set PNOR_CRE_MODE_SEL_CONTROL.fsel = 0x2 */ 44 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2ec), 45 MODE_SEL_CONTROL_FSEL_MASK, 46 MODE_SEL_CONTROL_FSEL_MODE2); 47 48 /* Set PNOR_CS_2_N_MODE_SEL_CONTROL.fsel = 0x2 */ 49 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f0), 50 MODE_SEL_CONTROL_FSEL_MASK, 51 MODE_SEL_CONTROL_FSEL_MODE2); 52 53 /* Set PNOR_CS_1_N_MODE_SEL_CONTROL.fsel = 0x2 */ 54 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f4), 55 MODE_SEL_CONTROL_FSEL_MASK, 56 MODE_SEL_CONTROL_FSEL_MODE2); 57 58 /* Set PNOR_CS_0_N_MODE_SEL_CONTROL.fsel = 0x2 */ 59 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f8), 60 MODE_SEL_CONTROL_FSEL_MASK, 61 MODE_SEL_CONTROL_FSEL_MODE2); 62 63 /* Set PNOR_WE_N_MODE_SEL_CONTROL.fsel = 0x2 */ 64 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2fc), 65 MODE_SEL_CONTROL_FSEL_MASK, 66 MODE_SEL_CONTROL_FSEL_MODE2); 67 68 /* Set PNOR_OE_N_MODE_SEL_CONTROL.fsel = 0x2 */ 69 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x300), 70 MODE_SEL_CONTROL_FSEL_MASK, 71 MODE_SEL_CONTROL_FSEL_MODE2); 72 73 /* Set PNOR_INTR_MODE_SEL_CONTROL.fsel = 0x2 */ 74 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x304), 75 MODE_SEL_CONTROL_FSEL_MASK, 76 MODE_SEL_CONTROL_FSEL_MODE2); 77 78 /* Set PNOR_DAT_x_MODE_SEL_CONTROL.fsel = 0x2 */ 79 for (i = 0; i < 0x40; i += 0x4) { 80 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x308 + i), 81 MODE_SEL_CONTROL_FSEL_MASK, 82 MODE_SEL_CONTROL_FSEL_MODE2); 83 } 84 85 /* Set NAND_CE1_N_MODE_SEL_CONTROL.fsel = 0x2 */ 86 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x348), 87 MODE_SEL_CONTROL_FSEL_MASK, 88 MODE_SEL_CONTROL_FSEL_MODE2); 89 90 /* Set NAND_CE0_N_MODE_SEL_CONTROL.fsel = 0x2 */ 91 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x34c), 92 MODE_SEL_CONTROL_FSEL_MASK, 93 MODE_SEL_CONTROL_FSEL_MODE2); 94 95 /* Set NAND_WE_N_MODE_SEL_CONTROL.fsel = 0x2 */ 96 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x350), 97 MODE_SEL_CONTROL_FSEL_MASK, 98 MODE_SEL_CONTROL_FSEL_MODE2); 99 100 /* Set NAND_WP_N_MODE_SEL_CONTROL.fsel = 0x2 */ 101 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x354), 102 MODE_SEL_CONTROL_FSEL_MASK, 103 MODE_SEL_CONTROL_FSEL_MODE2); 104 105 /* Set NAND_RE_N_MODE_SEL_CONTROL.fsel = 0x2 */ 106 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x358), 107 MODE_SEL_CONTROL_FSEL_MASK, 108 MODE_SEL_CONTROL_FSEL_MODE2); 109 110 /* Set NAND_RDY_BSY_N_MODE_SEL_CONTROL.fsel = 0x2 */ 111 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x35c), 112 MODE_SEL_CONTROL_FSEL_MASK, 113 MODE_SEL_CONTROL_FSEL_MODE2); 114 115 /* Set NAND_IOx_0_MODE_SEL_CONTROL.fsel = 0x2 */ 116 for (i = 0; i < 0x40; i += 0x4) { 117 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x360 + i), 118 MODE_SEL_CONTROL_FSEL_MASK, 119 MODE_SEL_CONTROL_FSEL_MODE2); 120 } 121 122 /* Set NAND_ALE_MODE_SEL_CONTROL.fsel = 0x2 */ 123 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x3a0), 124 MODE_SEL_CONTROL_FSEL_MASK, 125 MODE_SEL_CONTROL_FSEL_MODE2); 126 127 /* Set NAND_CLE_MODE_SEL_CONTROL.fsel = 0x2 */ 128 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x3a4), 129 MODE_SEL_CONTROL_FSEL_MASK, 130 MODE_SEL_CONTROL_FSEL_MODE2); 131 132 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x40), (7 << 1), 0x8); 133 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x44), (7 << 1), 0x8); 134 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x48), (7 << 1), 0x8); 135 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x4c), (7 << 1), 0x8); 136 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x50), (7 << 1), 0x8); 137 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x54), (7 << 1), 0x8); 138 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x58), (7 << 1), 0x8); 139 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x5c), (7 << 1), 0x8); 140 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x60), (7 << 1), 0x8); 141 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x64), (7 << 1), 0x8); 142 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x68), (7 << 1), 0x8); 143 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x6c), (7 << 1), 0x8); 144 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x70), (7 << 1), 0x8); 145 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x74), (7 << 1), 0x8); 146 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x78), (7 << 1), 0x8); 147 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x7c), (7 << 1), 0x8); 148 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x80), (7 << 1), 0x8); 149 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x84), (7 << 1), 0x8); 150 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x88), (7 << 1), 0x8); 151 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x8c), (7 << 1), 0x8); 152 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x90), (7 << 1), 0x8); 153 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x94), (7 << 1), 0x8); 154 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x98), (7 << 1), 0x8); 155 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x9c), (7 << 1), 0x8); 156 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0xa0), (7 << 1), 0x8); 157 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0xa4), (7 << 1), 0x8); 158 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0xa8), (7 << 1), 0x8); 159 160 INFO(" - pnor pinmux init done.\n"); 161 } 162 163 #if BL2_TEST_EXT_SRAM 164 #define SRAM_CHECKS_GRANUL 0x100000 165 #define SRAM_CHECKS_CNT 8 166 static unsigned int sram_checks[SRAM_CHECKS_CNT] = { 167 /* offset, magic */ 168 0xd00dfeed, 169 0xfadebabe, 170 0xc001d00d, 171 0xa5a5b5b5, 172 0x5a5a5b5b, 173 0xc5c5d5d5, 174 0x5c5c5d5d, 175 0xe5e5f5f5, 176 }; 177 #endif 178 179 static void brcm_stingray_pnor_sram_init(void) 180 { 181 unsigned int val, tmp; 182 #if BL2_TEST_EXT_SRAM 183 unsigned int off, i; 184 #endif 185 INFO(" - pnor sram init start.\n"); 186 187 /* Enable PNOR Clock */ 188 INFO(" -- enable pnor clock\n"); 189 mmio_write_32((uintptr_t)(PNOR_IDM_IO_CONTROL_DIRECT), 0x1); 190 udelay(500); 191 192 /* Reset PNOR */ 193 INFO(" -- reset pnor\n"); 194 mmio_setbits_32((uintptr_t)(PNOR_IDM_IO_RESET_CONTROL), 0x1); 195 udelay(500); 196 mmio_clrbits_32((uintptr_t)(PNOR_IDM_IO_RESET_CONTROL), 0x1); 197 udelay(500); 198 199 /* Configure slave address to chip-select mapping */ 200 INFO(" -- configure pnor slave address to chip-select mapping\n"); 201 /* 0x74000000-0x75ffffff => CS0 (32MB) */ 202 val = (0xfe << PNOR_ICFG_CS_x_MASK0_SHIFT); 203 val |= (0x74); 204 mmio_write_32((uintptr_t)(PNOR_ICFG_CS_0), val); 205 /* 0x76000000-0x77ffffff => CS1 (32MB) */ 206 val = (0xfe << PNOR_ICFG_CS_x_MASK0_SHIFT); 207 val |= (0x76); 208 mmio_write_32((uintptr_t)(PNOR_ICFG_CS_1), val); 209 /* 0xffffffff-0xffffffff => CS2 (0MB) */ 210 val = (0x00 << PNOR_ICFG_CS_x_MASK0_SHIFT); 211 val |= (0xff); 212 mmio_write_32((uintptr_t)(PNOR_ICFG_CS_2), val); 213 214 /* Print PNOR ID */ 215 tmp = 0x0; 216 val = mmio_read_32((uintptr_t)(PNOR_REG_PERIPH_ID0)); 217 tmp |= (val & PNOR_REG_PERIPH_IDx_MASK); 218 val = mmio_read_32((uintptr_t)(PNOR_REG_PERIPH_ID1)); 219 tmp |= ((val & PNOR_REG_PERIPH_IDx_MASK) << 8); 220 val = mmio_read_32((uintptr_t)(PNOR_REG_PERIPH_ID2)); 221 tmp |= ((val & PNOR_REG_PERIPH_IDx_MASK) << 16); 222 val = mmio_read_32((uintptr_t)(PNOR_REG_PERIPH_ID3)); 223 tmp |= ((val & PNOR_REG_PERIPH_IDx_MASK) << 24); 224 INFO(" -- pnor primecell_id = 0x%x\n", tmp); 225 226 /* PNOR set_cycles */ 227 #ifdef EMULATION_SETUP 228 val = 0x00129A44; 229 #else 230 val = 0x00125954; /* 0x00002DEF; */ 231 #endif 232 mmio_write_32((uintptr_t)(PNOR_REG_SET_CYCLES), val); 233 INFO(" -- pnor set_cycles = 0x%x\n", val); 234 235 /* PNOR set_opmode */ 236 val = 0x0; 237 #ifdef EMULATION_SETUP 238 /* TODO: Final values to be provided by DV folks */ 239 val &= ~(0x7 << 7); /* set_wr_bl */ 240 val &= ~(0x7 << 3); /* set_rd_bl */ 241 val &= ~(0x3); 242 val |= (0x1); /* set_mw */ 243 #else 244 /* TODO: Final values to be provided by DV folks */ 245 val &= ~(0x7 << 7); /* set_wr_bl */ 246 val &= ~(0x7 << 3); /* set_rd_bl */ 247 val &= ~(0x3); 248 val |= (0x1); /* set_mw */ 249 #endif 250 mmio_write_32((uintptr_t)(PNOR_REG_SET_OPMODE), val); 251 INFO(" -- pnor set_opmode = 0x%x\n", val); 252 253 #ifndef EMULATION_SETUP 254 /* Actual SRAM chip will require self-refresh */ 255 val = 0x1; 256 mmio_write_32((uintptr_t)(PNOR_REG_REFRESH_0), val); 257 INFO(" -- pnor refresh_0 = 0x%x\n", val); 258 #endif 259 260 #if BL2_TEST_EXT_SRAM 261 /* Check PNOR SRAM access */ 262 for (off = 0; off < NOR_SIZE; off += SRAM_CHECKS_GRANUL) { 263 i = (off / SRAM_CHECKS_GRANUL) % SRAM_CHECKS_CNT; 264 val = sram_checks[i]; 265 INFO(" -- pnor sram write addr=0x%lx value=0x%lx\n", 266 (unsigned long)(NOR_BASE_ADDR + off), 267 (unsigned long)val); 268 mmio_write_32((uintptr_t)(NOR_BASE_ADDR + off), val); 269 } 270 tmp = 0; 271 for (off = 0; off < NOR_SIZE; off += SRAM_CHECKS_GRANUL) { 272 i = (off / SRAM_CHECKS_GRANUL) % SRAM_CHECKS_CNT; 273 val = mmio_read_32((uintptr_t)(NOR_BASE_ADDR + off)); 274 INFO(" -- pnor sram read addr=0x%lx value=0x%lx\n", 275 (unsigned long)(NOR_BASE_ADDR + off), 276 (unsigned long)val); 277 if (val == sram_checks[i]) 278 tmp++; 279 } 280 INFO(" -- pnor sram checks pass=%d total=%d\n", 281 tmp, (NOR_SIZE / SRAM_CHECKS_GRANUL)); 282 283 if (tmp != (NOR_SIZE / SRAM_CHECKS_GRANUL)) { 284 INFO(" - pnor sram init failed.\n"); 285 while (1) 286 ; 287 } else { 288 INFO(" - pnor sram init done.\n"); 289 } 290 #endif 291 } 292 293 void ext_sram_init(void) 294 { 295 INFO("%s start.\n", __func__); 296 297 brcm_stingray_pnor_pinmux_init(); 298 299 brcm_stingray_pnor_sram_init(); 300 301 INFO("%s done.\n", __func__); 302 } 303