1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * Copyright (C) 2021 Semihalf. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * https://spdx.org/licenses 7 */ 8 9 #include <armada_common.h> 10 #include <mvebu_def.h> 11 12 /* 13 * If bootrom is currently at BLE there's no need to include the memory 14 * maps structure at this point 15 */ 16 #ifndef IMAGE_BLE 17 18 /***************************************************************************** 19 * AMB Configuration 20 ***************************************************************************** 21 */ 22 struct addr_map_win amb_memory_map_cp0[] = { 23 /* CP0 SPI1 CS0 Direct Mode access */ 24 {0xef00, 0x1000000, AMB_SPI1_CS0_ID}, 25 }; 26 27 struct addr_map_win amb_memory_map_cp1[] = { 28 /* CP1 SPI1 CS0 Direct Mode access */ 29 {0xe800, 0x1000000, AMB_SPI1_CS0_ID}, 30 }; 31 32 int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, 33 uintptr_t base) 34 { 35 switch (base) { 36 case MVEBU_CP_REGS_BASE(0): 37 *win = amb_memory_map_cp0; 38 *size = ARRAY_SIZE(amb_memory_map_cp0); 39 return 0; 40 case MVEBU_CP_REGS_BASE(1): 41 *win = amb_memory_map_cp1; 42 *size = ARRAY_SIZE(amb_memory_map_cp1); 43 return 0; 44 case MVEBU_CP_REGS_BASE(2): 45 default: 46 *size = 0; 47 *win = 0; 48 return 1; 49 } 50 } 51 #endif 52 53 /***************************************************************************** 54 * IO WIN Configuration 55 ***************************************************************************** 56 */ 57 struct addr_map_win io_win_memory_map[] = { 58 #if (CP_COUNT > 1) 59 /* SB (MCi0) internal regs */ 60 {0x00000000f4000000, 0x2000000, MCI_0_TID}, 61 /* SB (MCi0) PCIe0-2 on CP1 */ 62 {0x00000000e2000000, 0x7000000, MCI_0_TID}, 63 /* 64 * Due to lack of sufficient number of IO windows registers, 65 * below CP1 PCIE configuration must be performed in the 66 * later firmware stages. It should replace the MCI 0 indirect 67 * window, which becomes no longer needed. 68 */ 69 /* {0x0000000890000000, 0x30000000, MCI_0_TID}, */ 70 #if (CP_COUNT > 2) 71 /* SB (MCi1) internal regs */ 72 {0x00000000f6000000, 0x2000000, MCI_1_TID}, 73 /* SB (MCi1) PCIe0-2 on CP2 */ 74 {0x00000000e9000000, 0x6000000, MCI_1_TID}, 75 /* 76 * Due to lack of sufficient number of IO windows registers, 77 * below CP2 PCIE configuration must be performed in the 78 * later firmware stages. It should replace the MCI 1 indirect 79 * window, which becomes no longer needed. 80 */ 81 /* {0x00000008c0000000, 0x30000000, MCI_1_TID}, */ 82 #endif 83 #endif 84 #ifndef IMAGE_BLE 85 /* MCI 0 indirect window */ 86 {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID}, 87 /* MCI 1 indirect window */ 88 {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID}, 89 #endif 90 }; 91 92 /* Global Control Register - window default target */ 93 uint32_t marvell_get_io_win_gcr_target(int ap_index) 94 { 95 /* 96 * PIDI == iMCIP AP to SB internal MoChi connection. 97 * In other words CP0 98 */ 99 return PIDI_TID; 100 } 101 102 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, 103 uint32_t *size) 104 { 105 *win = io_win_memory_map; 106 if (*win == NULL) 107 *size = 0; 108 else 109 *size = ARRAY_SIZE(io_win_memory_map); 110 111 return 0; 112 } 113 114 #ifndef IMAGE_BLE 115 /***************************************************************************** 116 * IOB Configuration 117 ***************************************************************************** 118 */ 119 struct addr_map_win iob_memory_map_cp0[] = { 120 /* SPI1_CS0 (RUNIT) window */ 121 {0x00000000ef000000, 0x1000000, RUNIT_TID}, 122 /* PEX2_X1 window */ 123 {0x00000000e1000000, 0x1000000, PEX2_TID}, 124 /* PEX1_X1 window */ 125 {0x00000000e0000000, 0x1000000, PEX1_TID}, 126 /* PEX0_X4 window */ 127 {0x00000000c0000000, 0x20000000, PEX0_TID}, 128 {0x0000000800000000, 0x90000000, PEX0_TID}, 129 }; 130 131 struct addr_map_win iob_memory_map_cp1[] = { 132 /* SPI1_CS0 (RUNIT) window */ 133 {0x00000000e8000000, 0x1000000, RUNIT_TID}, 134 /* PEX2_X1 window */ 135 {0x00000000e6000000, 0x2000000, PEX2_TID}, 136 {0x00000008b0000000, 0x10000000, PEX2_TID}, 137 /* PEX1_X1 window */ 138 {0x00000000e4000000, 0x2000000, PEX1_TID}, 139 {0x00000008a0000000, 0x10000000, PEX1_TID}, 140 /* PEX0_X2 window */ 141 {0x00000000e2000000, 0x2000000, PEX0_TID}, 142 {0x0000000890000000, 0x10000000, PEX0_TID}, 143 }; 144 145 struct addr_map_win iob_memory_map_cp2[] = { 146 147 /* PEX2_X1 window */ 148 {0x00000000ed000000, 0x2000000, PEX2_TID}, 149 {0x00000008e0000000, 0x10000000, PEX2_TID}, 150 /* PEX1_X1 window */ 151 {0x00000000eb000000, 0x2000000, PEX1_TID}, 152 {0x00000008d0000000, 0x10000000, PEX1_TID}, 153 /* PEX0_X1 window */ 154 {0x00000000e9000000, 0x2000000, PEX0_TID}, 155 {0x00000008c0000000, 0x10000000, PEX0_TID}, 156 }; 157 158 int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, 159 uintptr_t base) 160 { 161 switch (base) { 162 case MVEBU_CP_REGS_BASE(0): 163 *win = iob_memory_map_cp0; 164 *size = ARRAY_SIZE(iob_memory_map_cp0); 165 return 0; 166 case MVEBU_CP_REGS_BASE(1): 167 *win = iob_memory_map_cp1; 168 *size = ARRAY_SIZE(iob_memory_map_cp1); 169 return 0; 170 case MVEBU_CP_REGS_BASE(2): 171 *win = iob_memory_map_cp2; 172 *size = ARRAY_SIZE(iob_memory_map_cp2); 173 return 0; 174 default: 175 *size = 0; 176 *win = 0; 177 return 1; 178 } 179 } 180 #endif 181 182 /***************************************************************************** 183 * CCU Configuration 184 ***************************************************************************** 185 */ 186 struct addr_map_win ccu_memory_map[] = { /* IO window */ 187 #ifdef IMAGE_BLE 188 {0x00000000f2000000, 0x6000000, IO_0_TID}, /* IO window */ 189 #else 190 #if LLC_SRAM 191 {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID}, 192 #endif 193 {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */ 194 {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ 195 {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */ 196 {0x0000002000000000, 0x70e000000, IO_0_TID}, /* IO for CV-OS */ 197 #endif 198 }; 199 200 uint32_t marvell_get_ccu_gcr_target(int ap) 201 { 202 return DRAM_0_TID; 203 } 204 205 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, 206 uint32_t *size) 207 { 208 *win = ccu_memory_map; 209 *size = ARRAY_SIZE(ccu_memory_map); 210 211 return 0; 212 } 213 214 #ifdef IMAGE_BLE 215 /***************************************************************************** 216 * SKIP IMAGE Configuration 217 ***************************************************************************** 218 */ 219 void *plat_get_skip_image_data(void) 220 { 221 /* No recovery button on CN-9130 board? */ 222 return NULL; 223 } 224 #endif 225