1 /* 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <plat/common/common_def.h> 12 13 /* CPU topology */ 14 #define PLAT_MAX_CORES_PER_CLUSTER U(4) 15 #define PLAT_CLUSTER_COUNT U(4) 16 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * PLAT_MAX_CORES_PER_CLUSTER) 17 18 #define PLAT_MAX_PWR_LVL U(1) 19 #define PLAT_MAX_RET_STATE U(1) 20 #define PLAT_MAX_OFF_STATE U(2) 21 22 /* Local power state for power domains in Run state. */ 23 #define SIGI_LOCAL_STATE_RUN U(0) 24 /* Local power state for retention. Valid only for CPU power domains */ 25 #define SIGI_LOCAL_STATE_RET U(1) 26 /* 27 * Local power state for OFF/power-down. Valid for CPU and cluster power 28 * domains. 29 */ 30 #define SIGI_LOCAL_STATE_OFF 2 31 32 /* 33 * Macros used to parse state information from State-ID if it is using the 34 * recommended encoding for State-ID. 35 */ 36 #define SIGI_LOCAL_PSTATE_WIDTH 4 37 #define SIGI_LOCAL_PSTATE_MASK ((1 << SIGI_LOCAL_PSTATE_WIDTH) - 1) 38 39 #define CACHE_WRITEBACK_SHIFT 6 40 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 41 42 /* xlat table v2 related to contants */ 43 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40) 44 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40) 45 #define MAX_XLAT_TABLES 8 46 #define MAX_MMAP_REGIONS 8 47 48 #define PLATFORM_STACK_SIZE 0x1000 49 50 /* physical memory related constants */ 51 #define SIGI_INTERLEAVE_DRAM_BASE 0x1000000000UL 52 #define SIGI_NON_INTER_DRAM_BASE 0x3000000000UL 53 #define SIGI_NS_DDR_SIZE (ULL(0x10) * SZ_1G) 54 #define SIGI_BL33_IMAGE_OFFSET 0x4000000 55 #define SIGI_BL33_DTB_OFFSET 0x2000000 56 57 #define SIGI_OCM_BASE 0x04000000 58 #define SIGI_OCM_SIZE SZ_32M 59 60 /* 61 * ARM-TF lives in SRAM, partition it here 62 */ 63 64 #define SHARED_RAM_BASE SIGI_OCM_BASE 65 #define SHARED_RAM_SIZE SZ_4K 66 67 #define SEC_SRAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 68 #define SEC_SRAM_SIZE SZ_512K 69 70 #define PLAT_SIGI_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 71 #define PLAT_SIGI_TRUSTED_MAILBOX_SIZE (8 + PLAT_SIGI_HOLD_SIZE) 72 #define PLAT_SIGI_HOLD_BASE (PLAT_SIGI_TRUSTED_MAILBOX_BASE + 8) 73 #define PLAT_SIGI_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 74 PLAT_SIGI_HOLD_ENTRY_SIZE) 75 #define PLAT_SIGI_HOLD_ENTRY_SHIFT 3 76 #define PLAT_SIGI_HOLD_ENTRY_SIZE (1 << PLAT_SIGI_HOLD_ENTRY_SHIFT) 77 #define PLAT_SIGI_HOLD_STATE_WAIT 0 78 #define PLAT_SIGI_HOLD_STATE_GO 1 79 80 /* 81 * BL3-1 specific defines. 82 * 83 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 84 * current BL3-1 debug size plus a little space for growth. 85 */ 86 #define BL31_BASE SEC_SRAM_BASE 87 #define BL31_SIZE (BL31_LIMIT - BL31_BASE) 88 #define BL31_LIMIT (BL31_BASE + SZ_512K) 89 90 #define BL32_BASE (SIGI_OCM_BASE + BL31_SIZE) 91 #define BL32_SIZE SZ_1M 92 #define BL32_LIMIT (BL32_BASE + BL32_SIZE) 93 94 /******************************************************************************* 95 * BL33 specific defines. 96 ******************************************************************************/ 97 #ifndef PRELOADED_BL33_BASE 98 # define PLAT_ARM_NS_IMAGE_BASE U(SIGI_NON_INTER_DRAM_BASE + SIGI_BL33_IMAGE_OFFSET) 99 # define PLAT_ARM_NS_DTB_BASE U(SIGI_NON_INTER_DRAM_BASE + SIGI_BL33_DTB_OFFSET) 100 #else 101 # define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE 102 #endif 103 104 /* 105 * UART related constants 106 */ 107 #define PLAT_SIGI_BOOT_UART_BASE 0x39050000 108 #define PLAT_SIGI_BOOT_UART_CLK_IN_HZ SIGI_UART0_CLK_IN_HZ 109 #define PLAT_SIGI_CONSOLE_BAUDRATE SIGI_UART0_BAUDRATE 110 111 #define PLAT_SIGI_UART1_BASE PLAT_SIGI_BOOT_UART_BASE 112 #define PLAT_SIGI_UART1_SIZE ULL(0x1000) 113 #define PLAT_SIGI_UART1_MMAP MAP_REGION_FLAT(PLAT_SIGI_UART1_BASE, \ 114 PLAT_SIGI_UART1_SIZE, \ 115 MT_DEVICE | MT_RW | \ 116 MT_NS | MT_PRIVILEGED) 117 118 #define DEVICE0_BASE 0x10000000 119 #define DEVICE0_SIZE 0x1C000000 120 #define DEVICE1_BASE 0x30000000 121 #define DEVICE1_SIZE 0x10000000 122 123 /* 124 * GIC related constants 125 */ 126 127 #define GICD_BASE 0x30B00000 128 #define GICC_BASE 0x30B10000 129 #define GICR_BASE 0x30B60000 130 131 #define SIGI_IRQ_SEC_SGI_0 8 132 #define SIGI_IRQ_SEC_SGI_1 9 133 #define SIGI_IRQ_SEC_SGI_2 10 134 #define SIGI_IRQ_SEC_SGI_3 11 135 #define SIGI_IRQ_SEC_SGI_4 12 136 #define SIGI_IRQ_SEC_SGI_5 13 137 #define SIGI_IRQ_SEC_SGI_6 14 138 #define SIGI_IRQ_SEC_SGI_7 15 139 140 #define PLATFORM_G1S_PROPS(grp) \ 141 INTR_PROP_DESC(SIGI_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 142 grp, GIC_INTR_CFG_EDGE), \ 143 INTR_PROP_DESC(SIGI_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 144 grp, GIC_INTR_CFG_EDGE), \ 145 INTR_PROP_DESC(SIGI_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 146 grp, GIC_INTR_CFG_EDGE), \ 147 INTR_PROP_DESC(SIGI_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 148 grp, GIC_INTR_CFG_EDGE), \ 149 INTR_PROP_DESC(SIGI_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 150 grp, GIC_INTR_CFG_EDGE), \ 151 INTR_PROP_DESC(SIGI_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 152 grp, GIC_INTR_CFG_EDGE), \ 153 INTR_PROP_DESC(SIGI_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 154 grp, GIC_INTR_CFG_EDGE), \ 155 INTR_PROP_DESC(SIGI_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 156 grp, GIC_INTR_CFG_EDGE) 157 158 #define PLATFORM_G0_PROPS(grp) 159 160 #define PLAT_SIGI_MHU_BASE 0x45000000 161 162 #define PLAT_SIGI_SCP_COM_SHARED_MEM_BASE 0x45400000 163 #define SCPI_CMD_GET_DRAMINFO 0x1 164 165 #define PLAT_SIGI_PRIMARY_CPU 0x0 166 #define PLAT_SIGI_PRIMARY_CPU_SHIFT 8 167 #define PLAT_SIGI_PRIMARY_CPU_BIT_WIDTH 6 168 169 #define PLAT_SPM_BUF_BASE (BL32_LIMIT - 32 * PLAT_SPM_BUF_SIZE) 170 #define PLAT_SPM_BUF_SIZE ULL(0x10000) 171 #define PLAT_SPM_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \ 172 PLAT_SPM_BUF_BASE, \ 173 PLAT_SPM_BUF_SIZE, \ 174 MT_RO_DATA | MT_SECURE | \ 175 MT_USER, PAGE_SIZE) 176 177 #define PLAT_SP_IMAGE_NS_BUF_BASE BL32_LIMIT 178 #define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x200000) 179 #define PLAT_SP_IMAGE_NS_BUF_MMAP MAP_REGION2(PLAT_SP_IMAGE_NS_BUF_BASE, \ 180 PLAT_SP_IMAGE_NS_BUF_BASE, \ 181 PLAT_SP_IMAGE_NS_BUF_SIZE, \ 182 MT_RW_DATA | MT_NS | \ 183 MT_USER, PAGE_SIZE) 184 185 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000) 186 #define PLAT_SP_IMAGE_STACK_SIZE (32 * PLAT_SP_IMAGE_STACK_PCPU_SIZE) 187 #define PLAT_SP_IMAGE_STACK_BASE (PLAT_SIGI_SP_HEAP_BASE + PLAT_SIGI_SP_HEAP_SIZE) 188 189 #define PLAT_SIGI_SP_IMAGE_SIZE ULL(0x200000) 190 #define PLAT_SIGI_SP_IMAGE_MMAP MAP_REGION2(BL32_BASE, BL32_BASE, \ 191 PLAT_SIGI_SP_IMAGE_SIZE, \ 192 MT_CODE | MT_SECURE | \ 193 MT_USER, PAGE_SIZE) 194 195 #define PLAT_SIGI_SP_HEAP_BASE (BL32_BASE + PLAT_SIGI_SP_IMAGE_SIZE) 196 #define PLAT_SIGI_SP_HEAP_SIZE ULL(0x800000) 197 198 #define PLAT_SIGI_SP_IMAGE_RW_MMAP MAP_REGION2(PLAT_SIGI_SP_HEAP_BASE, \ 199 PLAT_SIGI_SP_HEAP_BASE, \ 200 (PLAT_SIGI_SP_HEAP_SIZE + \ 201 PLAT_SP_IMAGE_STACK_SIZE), \ 202 MT_RW_DATA | MT_SECURE | \ 203 MT_USER, PAGE_SIZE) 204 205 #define PLAT_SIGI_SP_PRIV_BASE (PLAT_SP_IMAGE_STACK_BASE + \ 206 PLAT_SP_IMAGE_STACK_SIZE) 207 #define PLAT_SIGI_SP_PRIV_SIZE ULL(0x40000) 208 209 #define PLAT_SP_PRI 0x20 210 #define PLAT_PRI_BITS 2 211 #define PLAT_SPM_COOKIE_0 ULL(0) 212 #define PLAT_SPM_COOKIE_1 ULL(0) 213 214 /* Total number of memory regions with distinct properties */ 215 #define PLAT_SP_IMAGE_NUM_MEM_REGIONS 6 216 217 #define PLAT_SP_IMAGE_MMAP_REGIONS 30 218 #define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20 219 #define PLAT_SP_IMAGE_XLAT_SECTION_NAME "sp_xlat_table" 220 #define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME "sp_xlat_table" 221 222 #define PLAT_SIGI_PERIPH_BASE 0x25000000 223 #define PLAT_SIGI_PERIPH_SIZE ULL(0x4B000000) 224 #define PLAT_SIGI_PERIPH_MMAP MAP_REGION_FLAT(PLAT_SIGI_PERIPH_BASE, \ 225 PLAT_SIGI_PERIPH_SIZE, \ 226 MT_DEVICE | MT_RW | \ 227 MT_NS | MT_USER) 228 229 #endif /* PLATFORM_DEF_H */ 230