1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (C) 2024, Charleye <wangkart@aliyun.com> 4 * All rights reserved. 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <plat/common/common_def.h> 12 13 /* RAS */ 14 #define PLAT_RAS_PRI U(0x10) 15 #define PLAT_LUA_DSU_ERRIRQ U(33) 16 #define PLAT_LUA_DSU_FAULTIRQ U(34) 17 #define PLAT_LUA_CPU0_ERRIRQ U(39) 18 #define PLAT_LUA_CPU0_FAULTIRQ U(43) 19 #define PLAT_LUA_CPU1_ERRIRQ U(40) 20 #define PLAT_LUA_CPU1_FAULTIRQ U(44) 21 #define PLAT_LUA_CPU2_ERRIRQ U(41) 22 #define PLAT_LUA_CPU2_FAULTIRQ U(45) 23 #define PLAT_LUA_CPU3_ERRIRQ U(42) 24 #define PLAT_LUA_CPU3_FAULTIRQ U(46) 25 26 /* SDEI */ 27 #define PLAT_SDEI_CRITICAL_PRI U(0x20) 28 #define PLAT_SDEI_NORMAL_PRI U(0x30) 29 30 /* CPU topology */ 31 #define PLAT_MAX_CORES_PER_CLUSTER U(4) 32 #define PLAT_CLUSTER_COUNT U(1) 33 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * PLAT_MAX_CORES_PER_CLUSTER) 34 35 #define PLAT_MAX_PWR_LVL U(1) 36 #define PLAT_MAX_RET_STATE U(1) 37 #define PLAT_MAX_OFF_STATE U(2) 38 39 #define PLAT_LUA_FAB_PERIPH_PRIO U(0x50) 40 #define PLAT_LUA_FAB_PERIPH_IRQ U(179 + 32) 41 42 #define PLATFORM_FAB_PERIPH_G0_PROPS(grp) \ 43 INTR_PROP_DESC(PLAT_LUA_FAB_PERIPH_IRQ, PLAT_LUA_FAB_PERIPH_PRIO, \ 44 grp, GIC_INTR_CFG_LEVEL) 45 46 /* Local power state for power domains in Run state. */ 47 #define LUA_LOCAL_STATE_RUN U(0) 48 /* Local power state for retention. Valid only for CPU power domains */ 49 #define LUA_LOCAL_STATE_RET U(1) 50 /* 51 * Local power state for OFF/power-down. Valid for CPU and cluster power 52 * domains. 53 */ 54 #define LUA_LOCAL_STATE_OFF U(2) 55 56 /* 57 * Macros used to parse state information from State-ID if it is using the 58 * recommended encoding for State-ID. 59 */ 60 #define LUA_LOCAL_PSTATE_WIDTH U(4) 61 #define LUA_LOCAL_PSTATE_MASK ((1 << LUA_LOCAL_PSTATE_WIDTH) - 1) 62 63 #define CACHE_WRITEBACK_SHIFT U(6) 64 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 65 66 /* xlat table v2 related to contants */ 67 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40) 68 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40) 69 #define MAX_XLAT_TABLES U(8) 70 #define MAX_MMAP_REGIONS U(16) 71 72 #define PLATFORM_STACK_SIZE (1UL << 12) 73 74 /* physical memory related constants */ 75 #define LUA_DRAM_BASE ULL(0x100000000) 76 #define LUA_NS_DDR_SIZE (ULL(0x10) * SZ_1G) 77 #define LUA_BL31_IMG_OFFSET 0x00104000 78 #define LUA_BL32_IMG_OFFSET 0x04000000 79 #define LUA_BL33_IMG_OFFSET 0x00200000 80 81 #define LUA_IRAM_BASE 0x00400000 82 #define LUA_IRAM_SIZE SZ_64K 83 84 #define SHARED_RAM_BASE (LUA_DRAM_BASE + SZ_1M) 85 #define SHARED_RAM_SIZE SZ_4K 86 87 #define PLAT_LUA_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 88 #define PLAT_LUA_TRUSTED_MAILBOX_SIZE (8 + PLAT_LUA_HOLD_SIZE) 89 #define PLAT_LUA_HOLD_BASE (SHARED_RAM_BASE + 8) 90 #define PLAT_LUA_HOLD_SIZE (PLATFORM_CORE_COUNT * PLAT_LUA_HOLD_ENTRY_SIZE) 91 #define PLAT_LUA_HOLD_ENTRY_SHIFT U(3) 92 #define PLAT_LUA_HOLD_ENTRY_SIZE (1 << PLAT_LUA_HOLD_ENTRY_SHIFT) 93 #define PLAT_LUA_HOLD_STATE_WAIT U(0) 94 #define PLAT_LUA_HOLD_STATE_GO U(1) 95 96 /* 97 * BL3-1 specific defines. 98 * 99 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 100 * current BL3-1 debug size plus a little space for growth. 101 */ 102 #define BL31_BASE (LUA_DRAM_BASE + LUA_BL31_IMG_OFFSET) 103 #define BL31_SIZE SZ_256K 104 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 105 106 #define BL32_BASE (LUA_DRAM_BASE + LUA_BL32_IMG_OFFSET) 107 #define BL32_SIZE SZ_32M 108 #define BL32_LIMIT (BL32_BASE + BL32_SIZE) 109 110 /******************************************************************************* 111 * BL33 specific defines. 112 ******************************************************************************/ 113 #ifndef PRELOADED_BL33_BASE 114 # define PLAT_ARM_NS_IMAGE_BASE U(LUA_DRAM_BASE + LUA_BL33_IMG_OFFSET) 115 #else 116 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 117 #endif 118 119 /* Clock configuration */ 120 #ifdef LUA_FPGA 121 #define LUA_OSC24M_CLK_IN_HZ 10000000 122 #else 123 #define LUA_OSC24M_CLK_IN_HZ 24000000 124 #endif 125 126 /* UART configuration */ 127 #define LUA_UART_BAUDRATE 921600 128 #ifdef LUA_UART0_CONSOLE 129 #define LUA_UART_CLK_IN_HZ U(200000000) 130 #else 131 #define LUA_UART_CLK_IN_HZ LUA_OSC24M_CLK_IN_HZ 132 #endif 133 134 /* 135 * UART related constants 136 */ 137 #define PLAT_PRI_BITS U(3) 138 139 #define PLAT_LUA_UART0_BASE 0x00602000 140 #define PLAT_LUA_UART0_SIZE ULL(0x1000) 141 #define PLAT_LUA_UART0_MMAP MAP_REGION_FLAT(PLAT_LUA_UART0_BASE, \ 142 PLAT_LUA_UART0_SIZE, \ 143 MT_DEVICE | MT_RW | \ 144 MT_NS | MT_PRIVILEGED) 145 146 #define PLAT_LUA_UART1_PRIO U(0x40) 147 #define PLAT_LUA_UART1_IRQ U(196) 148 #define PLAT_LUA_UART1_BASE 0x0E403000 149 #define PLAT_LUA_UART1_SIZE ULL(0x1000) 150 #define PLAT_LUA_UART1_MMAP MAP_REGION_FLAT(PLAT_LUA_UART1_BASE, \ 151 PLAT_LUA_UART1_SIZE, \ 152 MT_DEVICE | MT_RW | \ 153 MT_NS | MT_PRIVILEGED) 154 155 #ifdef LUA_UART0_CONSOLE 156 #define PLAT_LUA_BOOT_UART_BASE PLAT_LUA_UART0_BASE 157 #define PLAT_LUA_BOOT_MMAP PLAT_LUA_UART0_MMAP 158 #else 159 #define PLAT_LUA_BOOT_UART_BASE PLAT_LUA_UART1_BASE 160 #define PLAT_LUA_BOOT_MMAP PLAT_LUA_UART1_MMAP 161 #endif 162 #define PLAT_LUA_BOOT_UART_CLK_IN_HZ LUA_UART_CLK_IN_HZ 163 #define PLAT_LUA_CONSOLE_BAUDRATE LUA_UART_BAUDRATE 164 165 #define DEVICE_BASE 0x04000000 166 #define DEVICE_SIZE SZ_512M 167 168 #define CPU_SYSCTL_BASE 0x08010000 169 #define CPU_SYSCTL_SIZE 0x1000 170 #define CA55_CORE_SW_RST_OFFSET 0xE0 171 172 /* 173 * GIC related constants 174 */ 175 #define GICD_BASE 0x08001000 176 #define GICD_SIZE 0x8000 177 #define GICC_BASE 0x08002000 178 179 #define LUA_SDEI_SGI_PRIVATE LUA_IRQ_SEC_SGI_0 180 181 #define LUA_IRQ_SEC_SGI_0 U(8) 182 #define LUA_IRQ_SEC_SGI_1 U(9) 183 #define LUA_IRQ_SEC_SGI_2 U(10) 184 #define LUA_IRQ_SEC_SGI_3 U(11) 185 #define LUA_IRQ_SEC_SGI_4 U(12) 186 #define LUA_IRQ_SEC_SGI_5 U(13) 187 #define LUA_IRQ_SEC_SGI_6 U(14) 188 #define LUA_IRQ_SEC_SGI_7 U(15) 189 190 #define PLATFORM_G1S_PROPS(grp) \ 191 INTR_PROP_DESC(LUA_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 192 grp, GIC_INTR_CFG_EDGE), \ 193 INTR_PROP_DESC(LUA_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 194 grp, GIC_INTR_CFG_EDGE), \ 195 INTR_PROP_DESC(LUA_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 196 grp, GIC_INTR_CFG_EDGE), \ 197 INTR_PROP_DESC(LUA_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 198 grp, GIC_INTR_CFG_EDGE), \ 199 INTR_PROP_DESC(LUA_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 200 grp, GIC_INTR_CFG_EDGE), \ 201 INTR_PROP_DESC(LUA_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 202 grp, GIC_INTR_CFG_EDGE), \ 203 INTR_PROP_DESC(LUA_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 204 grp, GIC_INTR_CFG_EDGE), \ 205 INTR_PROP_DESC(LUA_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 206 grp, GIC_INTR_CFG_EDGE) 207 208 #define PLATFORM_UART1_G0_PROPS(grp) \ 209 INTR_PROP_DESC(PLAT_LUA_UART1_IRQ, PLAT_LUA_UART1_PRIO, \ 210 grp, GIC_INTR_CFG_LEVEL) 211 212 #define PLATFORM_RAS_G0_PROPS(grp) \ 213 INTR_PROP_DESC(PLAT_LUA_DSU_ERRIRQ, PLAT_RAS_PRI, \ 214 grp, GIC_INTR_CFG_EDGE), \ 215 INTR_PROP_DESC(PLAT_LUA_DSU_FAULTIRQ, PLAT_RAS_PRI, \ 216 grp, GIC_INTR_CFG_EDGE), \ 217 INTR_PROP_DESC(PLAT_LUA_CPU0_ERRIRQ, PLAT_RAS_PRI, \ 218 grp, GIC_INTR_CFG_EDGE), \ 219 INTR_PROP_DESC(PLAT_LUA_CPU0_FAULTIRQ, PLAT_RAS_PRI, \ 220 grp, GIC_INTR_CFG_EDGE), \ 221 INTR_PROP_DESC(PLAT_LUA_CPU1_ERRIRQ, PLAT_RAS_PRI, \ 222 grp, GIC_INTR_CFG_EDGE), \ 223 INTR_PROP_DESC(PLAT_LUA_CPU1_FAULTIRQ, PLAT_RAS_PRI, \ 224 grp, GIC_INTR_CFG_EDGE), \ 225 INTR_PROP_DESC(PLAT_LUA_CPU2_ERRIRQ, PLAT_RAS_PRI, \ 226 grp, GIC_INTR_CFG_EDGE), \ 227 INTR_PROP_DESC(PLAT_LUA_CPU2_FAULTIRQ, PLAT_RAS_PRI, \ 228 grp, GIC_INTR_CFG_EDGE), \ 229 INTR_PROP_DESC(PLAT_LUA_CPU3_ERRIRQ, PLAT_RAS_PRI, \ 230 grp, GIC_INTR_CFG_EDGE), \ 231 INTR_PROP_DESC(PLAT_LUA_CPU3_FAULTIRQ, PLAT_RAS_PRI, \ 232 grp, GIC_INTR_CFG_EDGE) 233 234 #define PLAT_LUA_PRIMARY_CPU 0x0 235 #define PLAT_LUA_PRIMARY_CPU_SHIFT 8 236 #define PLAT_LUA_PRIMARY_CPU_BIT_WIDTH 6 237 238 #endif /* PLATFORM_DEF_H */ 239