1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (C) 2024, Charleye <wangkart@aliyun.com> 4 * All rights reserved. 5 */ 6 7 #ifndef LMT_DEF_H 8 #define LMT_DEF_H 9 10 #define PLATFORM_NAME "lambert virt platform" 11 12 /* Clock configuration */ 13 #define LMT_OSC24M_CLK_IN_HZ 24000000 14 15 /* UART configuration */ 16 #define LMT_UART0_BAUDRATE 115200 17 #define LMT_UART0_CLK_IN_HZ LMT_OSC24M_CLK_IN_HZ 18 19 unsigned int lmt_calc_core_pos(u_register_t mpidr); 20 void lmt_console_init(void); 21 void plat_lmt_gic_init(void); 22 void lmt_pwr_gic_on_finish(void); 23 void lmt_pwr_gic_off(void); 24 25 /* PMU register offsets for CPU*/ 26 enum { 27 CPU_CL0_C0_0 = 0x0214, 28 CPU_CL0_C0_1 = 0x0218, 29 CPU_CL0_C1_0 = 0x0220, 30 CPU_CL0_C1_1 = 0x0224, 31 CPU_CL0_C2_0 = 0x022c, 32 CPU_CL0_C2_1 = 0x0230, 33 CPU_CL0_C3_0 = 0x0238, 34 CPU_CL0_C3_1 = 0x023c, 35 CPU_CL1_C0_0 = 0x0240, 36 CPU_CL1_C0_1 = 0x0244, 37 CPU_CL1_C1_0 = 0x0248, 38 CPU_CL1_C1_1 = 0x024c, 39 CPU_CL1_C2_0 = 0x0250, 40 CPU_CL1_C2_1 = 0x0254, 41 CPU_CL1_C3_0 = 0x0258, 42 CPU_CL1_C3_1 = 0x025c, 43 }; 44 45 #define LMT_PMU_BASE 0x100000UL 46 47 #endif /* LMT_DEF_H */