Lines Matching defs:ret
187 int ret;
190 ret = request_intr_type_el3(ARM_IRQ_SEC_SGI_7, zynqmp_sgi7_irq);
191 if (ret) {
196 ret = request_intr_type_el3(IRQ_TTC3_1, ttc_fiq_handler);
197 if (ret)
201 return ret;
239 int32_t status = 0, ret = 0;
249 ret = 0;
252 ret = status;
257 return ret;
284 enum pm_ret_status ret;
306 ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
308 SMC_RET1(handle, (uint64_t)ret);
311 ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
313 SMC_RET1(handle, (uint64_t)ret);
322 ret = pm_req_wakeup(pm_arg[0], set_addr, address,
324 SMC_RET1(handle, (uint64_t)ret);
328 ret = pm_force_powerdown(pm_arg[0], pm_arg[1]);
329 SMC_RET1(handle, (uint64_t)ret);
332 ret = pm_abort_suspend(pm_arg[0]);
333 SMC_RET1(handle, (uint64_t)ret);
336 ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2]);
337 SMC_RET1(handle, (uint64_t)ret);
340 ret = pm_system_shutdown(pm_arg[0], pm_arg[1]);
341 SMC_RET1(handle, (uint64_t)ret);
344 ret = pm_req_node(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
345 SMC_RET1(handle, (uint64_t)ret);
348 ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2],
350 SMC_RET1(handle, (uint64_t)ret);
366 ret = pm_fpga_load(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
367 SMC_RET1(handle, (uint64_t)ret);
373 ret = pm_fpga_get_status(&value);
374 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
378 ret = pm_secure_rsaaes(pm_arg[0], pm_arg[1], pm_arg[2],
380 SMC_RET1(handle, (uint64_t)ret);
383 ret = pm_get_callbackdata(result, ARRAY_SIZE(result));
384 if (ret != PM_RET_SUCCESS) {
385 result[0] = ret;
395 ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2],
397 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
411 ret = pm_clock_enable(pm_arg[0]);
412 SMC_RET1(handle, (uint64_t)ret);
415 ret = pm_clock_disable(pm_arg[0]);
416 SMC_RET1(handle, (uint64_t)ret);
422 ret = pm_clock_getstate(pm_arg[0], &value);
423 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
427 ret = pm_clock_setdivider(pm_arg[0], pm_arg[1]);
428 SMC_RET1(handle, (uint64_t)ret);
434 ret = pm_clock_getdivider(pm_arg[0], &value);
435 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
439 ret = pm_clock_setparent(pm_arg[0], pm_arg[1]);
440 SMC_RET1(handle, (uint64_t)ret);
446 ret = pm_clock_getparent(pm_arg[0], &value);
447 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
455 ret = pm_set_suspend_mode(pm_arg[0]);
456 SMC_RET1(handle, (uint64_t)ret);
459 ret = pm_sha_hash(pm_arg[0], pm_arg[1], pm_arg[2],
461 SMC_RET1(handle, (uint64_t)ret);
464 ret = pm_rsa_core(pm_arg[0], pm_arg[1], pm_arg[2],
466 SMC_RET1(handle, (uint64_t)ret);
470 ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2],
472 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U),
480 ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3],
482 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
489 ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value);
490 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
494 ret = pm_pll_set_parameter(pm_arg[0], pm_arg[1], pm_arg[2]);
495 SMC_RET1(handle, (uint64_t)ret);
501 ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value);
502 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32U));
506 ret = pm_pll_set_mode(pm_arg[0], pm_arg[1]);
507 SMC_RET1(handle, (uint64_t)ret);
513 ret = pm_pll_get_mode(pm_arg[0], &mode);
514 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32U));
521 ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2],
523 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
537 ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value);
538 SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32U);
548 ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, 3U);
549 SMC_RET2(handle, (uint64_t)ret | (uint64_t)ret_payload[0] << 32U,
558 ret = pm_feature_check(pm_arg[0], &version, bit_mask,
560 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)version << 32U),
568 ret = pm_ipi_send_sync(primary_proc, payload, result,
570 SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U),