Lines Matching defs:pll

202  * @type: Topology type (mux/div1/div2/gate/pll/fixed factor).
2792 struct pm_pll *pll = pm_clock_get_pll(clock_id);
2794 if (pll) {
2795 *node_id = pll->nid;
2828 * @pll: PLL to be locked.
2836 enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll)
2838 if (pll == NULL) {
2843 if (pll->mode == PLL_FRAC_MODE) {
2844 return pm_pll_set_mode(pll->nid, PM_PLL_MODE_FRACTIONAL);
2847 return pm_pll_set_mode(pll->nid, PM_PLL_MODE_INTEGER);
2852 * @pll: PLL to be bypassed/reset.
2860 enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll)
2862 if (pll == NULL) {
2866 return pm_pll_set_mode(pll->nid, PM_PLL_MODE_RESET);
2871 * @pll: Pointer to the target PLL structure.
2880 enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll,
2886 if ((pll == NULL) || !state) {
2890 status = pm_pll_get_mode(pll->nid, &mode);
2906 * @pll: Target PLL structure.
2917 enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll,
2921 if (pll == NULL) {
2924 if (pll->pre_src == clock_id) {
2925 return pm_pll_set_parameter(pll->nid, PM_PLL_PARAM_PRE_SRC,
2928 if (pll->post_src == clock_id) {
2929 return pm_pll_set_parameter(pll->nid, PM_PLL_PARAM_POST_SRC,
2932 if (pll->div2 == clock_id) {
2933 return pm_pll_set_parameter(pll->nid, PM_PLL_PARAM_DIV2,
2942 * @pll: Target PLL structure.
2951 enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll,
2955 if (pll == NULL) {
2958 if (pll->pre_src == clock_id) {
2959 return pm_pll_get_parameter(pll->nid, PM_PLL_PARAM_PRE_SRC,
2962 if (pll->post_src == clock_id) {
2963 return pm_pll_get_parameter(pll->nid, PM_PLL_PARAM_POST_SRC,
2966 if (pll->div2 == clock_id) {
2967 return pm_pll_get_parameter(pll->nid, PM_PLL_PARAM_DIV2,
2970 if (pll->bypass == clock_id) {
2991 struct pm_pll *pll = pm_clock_get_pll(clock_id);
2993 if ((pll == NULL) || (mode != PLL_FRAC_MODE && mode != PLL_INT_MODE)) {
2996 pll->mode = mode;
3014 struct pm_pll *pll = pm_clock_get_pll(clock_id);
3016 if ((pll == NULL) || !mode) {
3019 *mode = pll->mode;