Lines Matching defs:nand
61 static void uniphier_nand_host_write(struct uniphier_nand *nand,
64 mmio_write_32(nand->host_base + DENALI_HOST_ADDR, addr);
65 mmio_write_32(nand->host_base + DENALI_HOST_DATA, data);
68 static uint32_t uniphier_nand_host_read(struct uniphier_nand *nand,
71 mmio_write_32(nand->host_base + DENALI_HOST_ADDR, addr);
72 return mmio_read_32(nand->host_base + DENALI_HOST_DATA);
75 static int uniphier_nand_block_isbad(struct uniphier_nand *nand, int block)
77 int page = nand->pages_per_block * block;
78 int column = nand->page_size;
84 if (block < ARRAY_SIZE(nand->bbt) &&
85 nand->bbt[block] != UNIPHIER_NAND_BBT_UNKNOWN)
86 return nand->bbt[block];
88 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 0);
90 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1);
92 uniphier_nand_host_write(nand, DENALI_MAP11_CMD, NAND_CMD_READ0);
93 uniphier_nand_host_write(nand, DENALI_MAP11_ADDR, column & 0xff);
94 uniphier_nand_host_write(nand, DENALI_MAP11_ADDR, (column >> 8) & 0xff);
95 uniphier_nand_host_write(nand, DENALI_MAP11_ADDR, page & 0xff);
96 uniphier_nand_host_write(nand, DENALI_MAP11_ADDR, (page >> 8) & 0xff);
97 if (!nand->two_row_addr_cycles)
98 uniphier_nand_host_write(nand, DENALI_MAP11_ADDR,
100 uniphier_nand_host_write(nand, DENALI_MAP11_CMD, NAND_CMD_READSTART);
103 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0);
106 bbm = uniphier_nand_host_read(nand, DENALI_MAP11_DATA);
111 if (block < ARRAY_SIZE(nand->bbt))
112 nand->bbt[block] = is_bad;
120 static int uniphier_nand_read_pages(struct uniphier_nand *nand, uintptr_t buf,
125 mmio_write_32(nand->reg_base + DENALI_ECC_ENABLE, 1);
126 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 1);
128 mmio_write_32(nand->reg_base + DENALI_INTR_STATUS0, -1);
131 mmio_write_32(nand->host_base + DENALI_HOST_ADDR,
138 mmio_write_32(nand->host_base + DENALI_HOST_DATA,
142 mmio_write_32(nand->host_base + DENALI_HOST_DATA, buf);
145 mmio_write_32(nand->host_base + DENALI_HOST_DATA, buf >> 32);
148 status = mmio_read_32(nand->reg_base + DENALI_INTR_STATUS0);
151 mmio_write_32(nand->reg_base + DENALI_DMA_ENABLE, 0);
162 static size_t __uniphier_nand_read(struct uniphier_nand *nand, int lba,
165 int pages_per_block = nand->pages_per_block;
166 int page_size = nand->page_size;
175 ret = uniphier_nand_block_isbad(nand, block);
186 ret = uniphier_nand_block_isbad(nand, block);
197 ret = uniphier_nand_read_pages(nand, p,
234 static int uniphier_nand_hw_init(struct uniphier_nand *nand)
238 for (i = 0; i < ARRAY_SIZE(nand->bbt); i++)
239 nand->bbt[i] = UNIPHIER_NAND_BBT_UNKNOWN;
241 nand->reg_base = nand->host_base + 0x100000;
243 nand->pages_per_block =
244 mmio_read_32(nand->reg_base + DENALI_PAGES_PER_BLOCK);
246 nand->page_size =
247 mmio_read_32(nand->reg_base + DENALI_DEVICE_MAIN_AREA_SIZE);
249 if (mmio_read_32(nand->reg_base + DENALI_TWO_ROW_ADDR_CYCLES) & BIT(0))
250 nand->two_row_addr_cycles = 1;
252 uniphier_nand_host_write(nand, DENALI_MAP10,