Lines Matching defs:host_base

97 static int uniphier_emmc_send_cmd(uintptr_t host_base,
104 	mmio_write_32(host_base + SDHCI_INT_STATUS, -1);
105 	mmio_write_32(host_base + SDHCI_SIGNAL_ENABLE, 0);
106 	mmio_write_32(host_base + SDHCI_ARGUMENT, cmd->cmdarg);
113 	mmio_write_16(host_base + SDHCI_TRANSFER_MODE, mode);
136 	mmio_write_16(host_base + SDHCI_COMMAND,
140 		stat = mmio_read_32(host_base + SDHCI_INT_STATUS);
145 			mmio_write_32(host_base + SDHCI_INT_STATUS, stat);
146 			dma_addr = mmio_read_32(host_base + SDHCI_DMA_ADDRESS);
147 			mmio_write_32(host_base + SDHCI_DMA_ADDRESS, dma_addr);
154 static int uniphier_emmc_switch_part(uintptr_t host_base, int part_num)
162 	return uniphier_emmc_send_cmd(host_base, &cmd);
165 static int uniphier_emmc_check_device_size(uintptr_t host_base,
176 	ret = uniphier_emmc_send_cmd(host_base, &cmd);
180 	csd40 = mmio_read_32(host_base + SDHCI_RESPONSE + 4);
181 	csd72 = mmio_read_32(host_base + SDHCI_RESPONSE + 8);
189 static int uniphier_emmc_load_image(uintptr_t host_base,
199 	mmio_write_32(host_base + SDHCI_DMA_ADDRESS, load_addr);
200 	mmio_write_16(host_base + SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(7, 512));
201 	mmio_write_16(host_base + SDHCI_BLOCK_COUNT, block_cnt);
203 	tmp = mmio_read_8(host_base + SDHCI_HOST_CONTROL);
206 	mmio_write_8(host_base + SDHCI_HOST_CONTROL, tmp);
208 	tmp = mmio_read_8(host_base + SDHCI_BLOCK_GAP_CONTROL);
210 	mmio_write_8(host_base + SDHCI_BLOCK_GAP_CONTROL, tmp);
217 	return uniphier_emmc_send_cmd(host_base, &cmd);
247 	uintptr_t host_base = uniphier_emmc_host.base;
257 	uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */
260 	mmio_write_8(host_base + SDHCI_SOFTWARE_RESET,
262 	while (mmio_read_8(host_base + SDHCI_SOFTWARE_RESET))
265 	ret = uniphier_emmc_check_device_size(host_base,
273 	ret = uniphier_emmc_send_cmd(host_base, &cmd);
278 	ret = uniphier_emmc_switch_part(host_base, 1);