Lines Matching defs:pll_id

53 static void set_pll_slow_mode(uint32_t pll_id)
55 	if (pll_id == PPLL_ID)
59 			      CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
62 static void set_pll_normal_mode(uint32_t pll_id)
64 	if (pll_id == PPLL_ID)
68 			      CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE);
71 static void set_pll_bypass(uint32_t pll_id)
73 	if (pll_id == PPLL_ID)
78 			      CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE);
81 static void _pll_suspend(uint32_t pll_id)
83 	set_pll_slow_mode(pll_id);
84 	set_pll_bypass(pll_id);
120  * pll_id: One of the values from enum plls_id
123 static void restore_pll(int pll_id, uint32_t *src)
126 	mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
128 	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK);
129 	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK);
130 	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]);
131 	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK);
132 	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK);
135 	mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK);
138 	while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) &
151  * pll_id: One of the values from enum plls_id
154 static void save_pll(uint32_t *dst, int pll_id)
159 		dst[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i));
218 static void set_plls_nobypass(uint32_t pll_id)
220 	if (pll_id == PPLL_ID)
224 		mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3),
228 static void _pll_resume(uint32_t pll_id)
230 	set_plls_nobypass(pll_id);
231 	set_pll_normal_mode(pll_id);