Lines Matching defs:cpu_id
474 static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id)
476 assert(cpu_id < PLATFORM_CORE_COUNT);
477 return core_pm_cfg_info[cpu_id];
480 static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value)
482 assert(cpu_id < PLATFORM_CORE_COUNT);
483 core_pm_cfg_info[cpu_id] = value;
485 flush_dcache_range((uintptr_t)&core_pm_cfg_info[cpu_id],
490 static int cpus_power_domain_on(uint32_t cpu_id)
493 uint32_t cpu_pd = PD_CPUL0 + cpu_id;
502 cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id);
506 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
510 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 0);
517 WARN("%s: cpu%d is not in off,!\n", __func__, cpu_id);
521 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
529 static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg)
534 cpu_pd = PD_CPUL0 + cpu_id;
539 if (check_cpu_wfie(cpu_id, CKECK_WFEI_MSK))
543 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
546 set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg);
549 set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg);
554 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
564 uint32_t cpu_id = plat_my_core_pos();
567 assert(cpu_id < PLATFORM_CORE_COUNT);
570 if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT) {
579 clst_st_chk_msk = clst_st_msk & ~(BIT(cpu_id));
608 uint32_t cpu_id = plat_my_core_pos();
611 assert(cpu_id < PLATFORM_CORE_COUNT);
614 if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT)
648 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
650 assert(cpu_id < PLATFORM_CORE_COUNT);
651 assert(cpuson_flags[cpu_id] == 0);
652 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG;
653 cpuson_entry_point[cpu_id] = entrypoint;
656 cpus_power_domain_on(cpu_id);
663 uint32_t cpu_id = plat_my_core_pos();
665 cpus_power_domain_off(cpu_id, core_pwr_wfi);
682 uint32_t cpu_id = plat_my_core_pos();
684 assert(cpu_id < PLATFORM_CORE_COUNT);
685 assert(cpuson_flags[cpu_id] == 0);
686 cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN;
687 cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint();
690 cpus_power_domain_off(cpu_id, core_pwr_wfi_int);
706 uint32_t cpu_id = plat_my_core_pos();
708 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
725 uint32_t cpu_id = plat_my_core_pos();
728 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE);