Lines Matching defs:sdram_params

185 		struct rk3399_sdram_params *sdram_params,
189 	uint32_t rank = sdram_params->ch[ch].rank;
193 	if (sdram_params->dramtype == LPDDR4)
202 		if (sdram_params->dramtype == LPDDR4) {
207 		} else if (sdram_params->dramtype == LPDDR3) {
210 		} else if (sdram_params->dramtype == DDR3) {
430 		struct rk3399_sdram_params *sdram_params,
434 	struct rk3399_sdram_channel *ch = &sdram_params->ch[channel];
453 		struct rk3399_sdram_params *sdram_params)
458 		struct rk3399_sdram_channel *info = &sdram_params->ch[i];
461 		if (sdram_params->ch[i].col == 0)
475 		if (sdram_params->ch[i].rank == 1)
479 	DDR_STRIDE(sdram_params->stride);
490 		struct rk3399_sdram_params *sdram_params)
492 	const uint32_t *params_ctl = sdram_params->pctl_regs.denali_ctl;
493 	const uint32_t *params_pi = sdram_params->pi_regs.denali_pi;
494 	const struct rk3399_ddr_publ_regs *phy_regs = &sdram_params->phy_regs;
547 		struct rk3399_sdram_params *sdram_params)
562 	ch_count = sdram_params->num_channels;
570 		if (sdram_params->dramtype != LPDDR4) {
576 		if (data_training(ch, sdram_params, PI_FULL_TRAINING))
588 		struct rk3399_sdram_params *sdram_params)
628 					   sdram_params->rx_cal_dqs[0][byte]);
647 					   sdram_params->rx_cal_dqs[1][byte]);
696 	struct rk3399_sdram_params *sdram_params = &sdram_config;
703 	phy_regs = &sdram_params->phy_regs;
704 	params_ctl = sdram_params->pctl_regs.denali_ctl;
705 	params_pi = sdram_params->pi_regs.denali_pi;
717 	sdram_params->ddr_freq = ((fbdiv * 24) /
720 	INFO("sdram_params->ddr_freq = %d\n", sdram_params->ddr_freq);
721 	sdram_params->odt = (((mmio_read_32(PHY_REG(0, 5)) >> 16) &
745 	for (ch = 0; ch < sdram_params->num_channels; ch++) {
747 			sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) &
785 	struct rk3399_sdram_params *sdram_params = &sdram_config;
811 	for (channel = 0; channel < sdram_params->num_channels; channel++) {
817 		if (sdram_params->dramtype == LPDDR4) {
818 			phy_dll_bypass_set(channel, sdram_params->ddr_freq);
820 		pctl_cfg(channel, sdram_params);
824 		if (sdram_params->ch[channel].col)
828 	if (pctl_start(channel_mask, sdram_params) < 0)
831 	for (channel = 0; channel < sdram_params->num_channels; channel++) {
833 		if (sdram_params->dramtype == LPDDR3)
840 		if (sdram_params->dramtype != LPDDR4 &&
841 		    data_training(channel, sdram_params, PI_FULL_TRAINING))
844 		set_ddrconfig(sdram_params, channel,
845 			      sdram_params->ch[channel].ddrconfig);
848 	dram_all_config(sdram_params);
851 	dram_switch_to_next_index(sdram_params);