Lines Matching defs:nmhz
206 uint32_t nmhz = timing_config->freq;
212 pdram_timing->mhz = nmhz;
215 if (nmhz <= 330)
217 else if (nmhz <= 400)
219 else if (nmhz <= 533)
221 else if (nmhz <= 666)
223 else if (nmhz <= 800)
225 else if (nmhz <= 933)
231 if (nmhz < 300) {
271 pdram_timing->trstl = ((DDR3_TRSTL * nmhz + 999) / 1000);
272 pdram_timing->trsth = ((DDR3_TRSTH * nmhz + 999) / 1000);
274 pdram_timing->trefi = ((DDR3_TREFI_7_8_US * nmhz + 999) / 1000);
279 tmp = ((DDR3_TWR * nmhz + 999) / 1000);
296 tmp = ((DDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000);
299 (((ddr3_trc_tfaw[ddr_speed_bin] >> 8) * nmhz + 999) / 1000);
300 tmp = ((DDR3_TRRD * nmhz + 999) / 1000);
303 tmp = ((DDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000);
307 pdram_timing->tras_min = ((DDR3_TRAS * nmhz + (nmhz >> 1) + 999)
310 (((ddr3_trc_tfaw[ddr_speed_bin] & 0x0ff) * nmhz + 999)
323 pdram_timing->trfc = (tmp * nmhz + 999) / 1000;
324 pdram_timing->txsnr = max(5, (((tmp + 10) * nmhz + 999) / 1000));
328 tmp = ((DDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000);
330 tmp = ((DDR3_TXPDLL * nmhz + 999) / 1000);
333 if (nmhz >= 533)
334 tmp = ((DDR3_TCKE_533MHZ * nmhz + 999) / 1000);
336 tmp = ((DDR3_TCKE_400MHZ * nmhz + (nmhz >> 1) + 999) / 1000);
339 tmp = ((DDR3_TCKSRE * nmhz + 999) / 1000);
343 tmp = ((DDR3_TMOD * nmhz + 999) / 1000);
350 tmp = ((DDR3_TZQINIT * nmhz + 999) / 1000);
352 tmp = ((DDR3_TZQCS * nmhz + 999) / 1000);
354 tmp = ((DDR3_TZQOPER * nmhz + 999) / 1000);
359 pdram_timing->twlo = ((DDR3_TWLO * nmhz + (nmhz >> 1) + 999) / 1000);
423 uint32_t nmhz = timing_config->freq;
428 pdram_timing->mhz = nmhz;
436 if (nmhz <= 266) {
440 } else if (nmhz <= 333) {
444 } else if (nmhz <= 400) {
448 } else if (nmhz <= 466) {
480 pdram_timing->tinit1 = (LPDDR2_TINIT1 * nmhz + 999) / 1000;
482 pdram_timing->tinit3 = (LPDDR2_TINIT3 * nmhz + 999) / 1000;
483 pdram_timing->tinit4 = (LPDDR2_TINIT4 * nmhz + 999) / 1000;
484 pdram_timing->tinit5 = (LPDDR2_TINIT5 * nmhz + 999) / 1000;
486 pdram_timing->trsth = (LPDDR2_TRSTH * nmhz + 999) / 1000;
492 pdram_timing->trefi = (LPDDR2_TREFI_3_9_US * nmhz + 999)
495 pdram_timing->trefi = (LPDDR2_TREFI_7_8_US * nmhz + 999)
498 tmp = ((LPDDR2_TRCD * nmhz + 999) / 1000);
503 trppb_tmp = ((LPDDR2_TRP_PB * nmhz + 999) / 1000);
510 trp_tmp = ((LPDDR2_TRP_AB_8_BANK * nmhz + 999) / 1000);
513 twr_tmp = ((LPDDR2_TWR * nmhz + 999) / 1000);
519 tmp = ((LPDDR2_TRTP * nmhz + (nmhz >> 1) + 999) / 1000);
521 tras_tmp = ((LPDDR2_TRAS * nmhz + 999) / 1000);
524 pdram_timing->tras_max = ((LPDDR2_TRAS_MAX * nmhz + 999) / 1000);
526 tmp = ((LPDDR2_TRRD * nmhz + 999) / 1000);
530 if (nmhz > 200)
531 tmp = ((LPDDR2_TWTR_GREAT_200MHZ * nmhz + (nmhz >> 1) +
534 tmp = ((LPDDR2_TWTR_LITTLE_200MHZ * nmhz + 999) / 1000);
537 if (nmhz <= 200)
538 pdram_timing->tfaw = (LPDDR2_TFAW_LITTLE_200MHZ * nmhz + 999)
541 pdram_timing->tfaw = (LPDDR2_TFAW_GREAT_200MHZ * nmhz + 999)
546 (LPDDR2_TRFC_8GBIT * nmhz + 999) / 1000;
547 tmp = (((LPDDR2_TRFC_8GBIT + 10) * nmhz + 999) / 1000);
550 (LPDDR2_TRFC_4GBIT * nmhz + 999) / 1000;
551 tmp = (((LPDDR2_TRFC_4GBIT + 10) * nmhz + 999) / 1000);
558 pdram_timing->tdqsck = ((LPDDR2_TDQSCK_MIN * nmhz + (nmhz >> 1))
561 ((LPDDR2_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999)
564 tmp = ((LPDDR2_TXP * nmhz + (nmhz >> 1) + 999) / 1000);
569 tmp = ((LPDDR2_TCKESR * nmhz + 999) / 1000);
578 pdram_timing->tzqinit = (LPDDR2_TZQINIT * nmhz + 999) / 1000;
579 tmp = ((LPDDR2_TZQCS * nmhz + 999) / 1000);
581 tmp = ((LPDDR2_TZQCL * nmhz + 999) / 1000);
583 tmp = ((LPDDR2_TZQRESET * nmhz + 999) / 1000);
663 uint32_t nmhz = timing_config->freq;
668 pdram_timing->mhz = nmhz;
678 if (nmhz <= 400) {
682 } else if (nmhz <= 533) {
686 } else if (nmhz <= 600) {
690 } else if (nmhz <= 667) {
694 } else if (nmhz <= 733) {
698 } else if (nmhz <= 800) {
702 } else if (nmhz <= 933) {
755 pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000;
757 pdram_timing->tinit3 = (LPDDR3_TINIT3 * nmhz + 999) / 1000;
758 pdram_timing->tinit4 = (LPDDR3_TINIT4 * nmhz + 999) / 1000;
759 pdram_timing->tinit5 = (LPDDR3_TINIT5 * nmhz + 999) / 1000;
761 pdram_timing->trsth = (LPDDR3_TRSTH * nmhz + 999) / 1000;
763 pdram_timing->trefi = (LPDDR3_TREFI_3_9_US * nmhz + 999) / 1000;
765 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000);
767 trppb_tmp = ((LPDDR3_TRP_PB * nmhz + 999) / 1000);
770 trp_tmp = ((LPDDR3_TRP_AB * nmhz + 999) / 1000);
773 twr_tmp = ((LPDDR3_TWR * nmhz + 999) / 1000);
791 tmp = ((LPDDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000);
793 tras_tmp = ((LPDDR3_TRAS * nmhz + 999) / 1000);
797 tmp = ((LPDDR3_TRRD * nmhz + 999) / 1000);
800 tmp = ((LPDDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000);
802 pdram_timing->trtw = ((LPDDR3_TRTW * nmhz + 999) / 1000);
803 pdram_timing->tras_max = ((LPDDR3_TRAS_MAX * nmhz + 999) / 1000);
804 tmp = (LPDDR3_TFAW * nmhz + 999) / 1000;
808 (LPDDR3_TRFC_8GBIT * nmhz + 999) / 1000;
809 tmp = (((LPDDR3_TRFC_8GBIT + 10) * nmhz + 999) / 1000);
812 (LPDDR3_TRFC_4GBIT * nmhz + 999) / 1000;
813 tmp = (((LPDDR3_TRFC_4GBIT + 10) * nmhz + 999) / 1000);
819 ((LPDDR3_TDQSCK_MIN * nmhz + (nmhz >> 1))
822 ((LPDDR3_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999)
825 tmp = ((LPDDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000);
828 tmp = ((LPDDR3_TCKE * nmhz + (nmhz >> 1) + 999) / 1000);
830 tmp = ((LPDDR3_TCKESR * nmhz + 999) / 1000);
836 tmp = ((LPDDR3_TMRD * nmhz + 999) / 1000);
839 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000);
842 pdram_timing->todton = (LPDDR3_TODTON * nmhz + (nmhz >> 1) + 999)
845 pdram_timing->tzqinit = (LPDDR3_TZQINIT * nmhz + 999) / 1000;
847 ((LPDDR3_TZQCS * nmhz + 999) / 1000);
849 ((LPDDR3_TZQCL * nmhz + 999) / 1000);
850 tmp = ((LPDDR3_TZQRESET * nmhz + 999) / 1000);
853 pdram_timing->twlmrd = (LPDDR3_TWLMRD * nmhz + 999) / 1000;
854 pdram_timing->twlo = (LPDDR3_TWLO * nmhz + 999) / 1000;
855 pdram_timing->twldqsen = (LPDDR3_TWLDQSEN * nmhz + 999) / 1000;
862 pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000;
863 pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000;
867 pdram_timing->tfc_long = (LPDDR3_TFC_LONG * nmhz + 999) / 1000;
959 uint32_t nmhz = timing_config->freq;
964 pdram_timing->mhz = nmhz;
983 if (nmhz <= 266) {
989 } else if (nmhz <= 533) {
1001 } else if (nmhz <= 800) {
1013 } else if (nmhz <= 1066) {
1025 } else if (nmhz <= 1333) {
1039 } else if (nmhz <= 1600) {
1053 } else if (nmhz <= 1866) {
1155 pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000;
1156 pdram_timing->tinit2 = (LPDDR4_TINIT2 * nmhz + 999) / 1000;
1157 pdram_timing->tinit3 = (LPDDR4_TINIT3 * nmhz + 999) / 1000;
1158 pdram_timing->tinit4 = (LPDDR4_TINIT4 * nmhz + 999) / 1000;
1159 pdram_timing->tinit5 = (LPDDR4_TINIT5 * nmhz + 999) / 1000;
1160 pdram_timing->trstl = (LPDDR4_TRSTL * nmhz + 999) / 1000;
1161 pdram_timing->trsth = (LPDDR4_TRSTH * nmhz + 999) / 1000;
1163 pdram_timing->trefi = (LPDDR4_TREFI_3_9_US * nmhz + 999) / 1000;
1165 tmp = ((LPDDR4_TRCD * nmhz + 999) / 1000);
1167 trppb_tmp = ((LPDDR4_TRP_PB * nmhz + 999) / 1000);
1170 trp_tmp = ((LPDDR4_TRP_AB * nmhz + 999) / 1000);
1173 tras_tmp = ((LPDDR4_TRAS * nmhz + 999) / 1000);
1177 tmp = ((LPDDR4_TRRD * nmhz + 999) / 1000);
1184 tmp = ((LPDDR4_TWTR * nmhz + 999) / 1000);
1186 pdram_timing->trtw = ((LPDDR4_TRTW * nmhz + 999) / 1000);
1187 pdram_timing->tras_max = ((LPDDR4_TRAS_MAX * nmhz + 999) / 1000);
1188 pdram_timing->tfaw = (LPDDR4_TFAW * nmhz + 999) / 1000;
1192 (LPDDR4_TRFC_12GBIT * nmhz + 999) / 1000;
1193 tmp = (((LPDDR4_TRFC_12GBIT + 7) * nmhz + (nmhz >> 1) +
1197 (LPDDR4_TRFC_6GBIT * nmhz + 999) / 1000;
1198 tmp = (((LPDDR4_TRFC_6GBIT + 7) * nmhz + (nmhz >> 1) +
1202 (LPDDR4_TRFC_4GBIT * nmhz + 999) / 1000;
1203 tmp = (((LPDDR4_TRFC_4GBIT + 7) * nmhz + (nmhz >> 1) +
1209 pdram_timing->tdqsck = ((LPDDR4_TDQSCK_MIN * nmhz +
1210 (nmhz >> 1)) / 1000);
1211 pdram_timing->tdqsck_max = ((LPDDR4_TDQSCK_MAX * nmhz +
1212 (nmhz >> 1) + 999) / 1000);
1215 tmp = ((LPDDR4_TXP * nmhz + (nmhz >> 1) + 999) / 1000);
1217 tmp = ((LPDDR4_TCKE * nmhz + (nmhz >> 1) + 999) / 1000);
1219 tmp = ((LPDDR4_TESCKE * nmhz +
1220 ((nmhz * 3) / 4) +
1223 tmp = ((LPDDR4_TSR * nmhz + 999) / 1000);
1225 tmp = ((LPDDR4_TCMDCKE * nmhz +
1226 ((nmhz * 3) / 4) +
1229 pdram_timing->tcscke = ((LPDDR4_TCSCKE * nmhz +
1230 ((nmhz * 3) / 4) +
1232 tmp = ((LPDDR4_TCKELCS * nmhz + 999) / 1000);
1234 pdram_timing->tcsckeh = ((LPDDR4_TCSCKEH * nmhz +
1235 ((nmhz * 3) / 4) +
1237 tmp = ((LPDDR4_TCKEHCS * nmhz +
1238 (nmhz >> 1) + 999) / 1000);
1240 tmp = ((LPDDR4_TMRWCKEL * nmhz + 999) / 1000);
1242 tmp = ((LPDDR4_TCKELCMD * nmhz + (nmhz >> 1) +
1245 tmp = ((LPDDR4_TCKEHCMD * nmhz + (nmhz >> 1) +
1248 tmp = ((LPDDR4_TCKELPD * nmhz + (nmhz >> 1) +
1251 tmp = ((LPDDR4_TCKCKEL * nmhz + (nmhz >> 1) +
1255 tmp = ((LPDDR4_TMRD * nmhz + 999) / 1000);
1260 pdram_timing->todton = (LPDDR4_TODTON * nmhz + (nmhz >> 1) + 999)
1263 pdram_timing->tzqcal = (LPDDR4_TZQCAL * nmhz + 999) / 1000;
1264 tmp = ((LPDDR4_TZQLAT * nmhz + 999) / 1000);
1266 tmp = ((LPDDR4_TZQRESET * nmhz + 999) / 1000);
1268 tmp = ((LPDDR4_TZQCKE * nmhz +
1269 ((nmhz * 3) / 4) +
1274 pdram_timing->twlo = (LPDDR4_TWLO * nmhz + 999) / 1000;
1277 pdram_timing->tcaent = (LPDDR4_TCAENT * nmhz + 999) / 1000;
1278 pdram_timing->tadr = (LPDDR4_TADR * nmhz + 999) / 1000;
1279 pdram_timing->tmrz = (LPDDR4_TMRZ * nmhz + (nmhz >> 1) + 999) / 1000;
1280 pdram_timing->tvref_long = (LPDDR4_TVREF_LONG * nmhz + 999) / 1000;
1281 pdram_timing->tvref_short = (LPDDR4_TVREF_SHORT * nmhz + 999) / 1000;
1283 pdram_timing->tvrcg_enable = (LPDDR4_TVRCG_ENABLE * nmhz +
1285 pdram_timing->tvrcg_disable = (LPDDR4_TVRCG_DISABLE * nmhz +
1288 pdram_timing->tfc_long = (LPDDR4_TFC_LONG * nmhz + 999) / 1000;
1289 tmp = (LPDDR4_TCKFSPE * nmhz + (nmhz >> 1) + 999) / 1000;
1291 tmp = (LPDDR4_TCKFSPX * nmhz + (nmhz >> 1) + 999) / 1000;