Lines Matching defs:tmp
106 uint32_t tmp;
112 tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1);
113 if (tmp)
117 tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) |
119 if (tmp == 0)
121 else if (tmp == 1)
123 else if (tmp == 3)
165 tmp = mr11_val & 0x7;
166 if ((tmp == 7) || (tmp == 0))
169 drv_config->dram_side_dq_odt = 240 / tmp;
171 tmp = (mr11_val >> 4) & 0x7;
172 if ((tmp == 7) || (tmp == 0))
175 drv_config->dram_side_ca_odt = 240 / tmp;
363 uint32_t tmp;
366 tmp = pdram_timing->cl;
367 if (tmp >= 14)
368 tmp = 8;
369 else if (tmp >= 10)
370 tmp = 6;
371 else if (tmp == 9)
372 tmp = 5;
373 else if (tmp == 8)
374 tmp = 4;
375 else if (tmp == 6)
376 tmp = 3;
378 tmp = 1;
380 tmp = 1;
383 return tmp;
452 uint32_t tmp, todtoff_min_ps;
461 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz);
463 tmp++;
464 return tmp;
470 uint32_t tmp, todtoff_max_ps;
479 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz);
481 tmp++;
482 return tmp;
490 uint32_t tmp, tmp1;
494 tmp = ((700000 + 10) * timing_config->freq +
496 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) +
498 mmio_write_32(CTL_REG(i, 5), tmp);
555 tmp = pdram_timing->tdal ? pdram_timing->tdal :
557 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp);
641 tmp = 4 << 24;
643 tmp = 8 << 24;
646 tmp = 2 << 24;
649 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp);
653 tmp =
657 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp);
666 tmp = get_pi_wrlat(pdram_timing, timing_config);
668 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0;
670 tmp = 0;
673 (tmp & 0x3f) << 16);
678 tmp = pdram_timing->cl +
682 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0;
684 tmp = pdram_timing->cl - pdram_timing->cwl;
687 (tmp & 0x3f) << 8);
706 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5;
707 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16);
710 tmp = tmp + 18;
711 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp);
717 tmp = 0;
719 tmp = tmp1 - 1;
721 tmp = tmp1 - 5;
723 tmp = tmp1 - 2;
725 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8);
730 tmp = pdram_timing->cl - 5;
732 tmp = pdram_timing->cl - 2;
733 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp);
742 uint32_t tmp, tmp1;
746 tmp =
748 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) +
750 mmio_write_32(CTL_REG(i, 9), tmp);
804 tmp = pdram_timing->tdal ? pdram_timing->tdal :
806 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8);
890 tmp = 4 << 24;
892 tmp = 8 << 24;
895 tmp = 2 << 24;
897 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp);
915 tmp = get_pi_wrlat(pdram_timing, timing_config);
917 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0;
919 tmp = 0;
922 (tmp & 0x3f) << 24);
927 tmp = pdram_timing->cl +
929 tmp--;
932 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0;
934 tmp = pdram_timing->cl - pdram_timing->cwl;
937 (tmp & 0x3f) << 16);
956 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5;
957 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16);
960 tmp = tmp + 18;
961 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp);
967 tmp = 0;
969 tmp = tmp1 - 1;
971 tmp = tmp1 - 5;
973 tmp = tmp1 - 2;
976 mmio_clrsetbits_32(CTL_REG(i, 314), 0xffu << 24, tmp << 24);
981 tmp = pdram_timing->cl - 5;
983 tmp = pdram_timing->cl - 2;
984 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16);
990 uint32_t i, tmp;
993 tmp = 0;
995 tmp = 1;
998 mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16);
999 mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp);
1028 uint32_t tmp, tmp1, tmp2;
1033 tmp = 4 * pdram_timing->trefi;
1034 mmio_write_32(PI_REG(i, 2), tmp);
1036 tmp = 2 * pdram_timing->trefi;
1037 mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp);
1039 mmio_clrsetbits_32(PI_REG(i, 7), 0xffffu << 16, tmp << 16);
1043 tmp = 2;
1045 tmp = 0;
1046 tmp = (pdram_timing->bl / 2) + 4 +
1047 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp +
1049 mmio_clrsetbits_32(PI_REG(i, 42), 0xff, tmp);
1052 tmp = get_pi_wrlat(pdram_timing, timing_config);
1053 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f, tmp);
1069 tmp = get_pi_todtoff_max(pdram_timing, timing_config);
1071 tmp << 24);
1079 tmp = tmp1 - tmp2;
1081 tmp = 0;
1083 tmp = 0;
1085 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 16, tmp << 16);
1096 tmp = tmp1 - tmp2;
1098 tmp = 0;
1100 tmp = pdram_timing->cl - pdram_timing->cwl;
1102 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 8, tmp << 8);
1104 tmp = get_pi_rdlat_adj(pdram_timing);
1105 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 16, tmp << 16);
1107 tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
1108 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 16, tmp << 16);
1110 tmp1 = tmp;
1112 tmp = 0;
1114 tmp = tmp1 - 1;
1116 tmp = tmp1 - 5;
1117 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 16, tmp << 16);
1122 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5;
1123 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff << 16, tmp << 16);
1125 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff, tmp + 18);
1134 tmp = tmp1 + 5;
1135 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 8, tmp << 8);
1137 tmp = 10000 / (1000000 / pdram_timing->mhz);
1139 tmp++;
1141 tmp = tmp + 1;
1143 tmp = tmp + 8;
1144 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 16, tmp << 16);
1186 tmp = pdram_timing->tras_max * 99 / 100;
1187 mmio_clrsetbits_32(PI_REG(i, 159), 0x1ffff, tmp);
1206 uint32_t tmp, tmp1, tmp2;
1211 tmp = 4 * pdram_timing->trefi;
1212 mmio_write_32(PI_REG(i, 4), tmp);
1214 tmp = 2 * pdram_timing->trefi;
1215 mmio_clrsetbits_32(PI_REG(i, 5), 0xffff, tmp);
1217 mmio_clrsetbits_32(PI_REG(i, 12), 0xffff, tmp);
1221 tmp = 2;
1223 tmp = 0;
1224 tmp = (pdram_timing->bl / 2) + 4 +
1225 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp +
1227 mmio_clrsetbits_32(PI_REG(i, 42), 0xff << 8, tmp << 8);
1230 tmp = get_pi_wrlat(pdram_timing, timing_config);
1232 tmp << 24);
1246 tmp = get_pi_todtoff_max(pdram_timing, timing_config);
1247 mmio_clrsetbits_32(PI_REG(i, 67), 0xff << 8, tmp << 8);
1255 tmp = tmp1 - tmp2;
1257 tmp = 0;
1259 tmp = 0;
1261 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 24, tmp << 24);
1272 tmp = tmp1 - tmp2;
1274 tmp = 0;
1276 tmp = pdram_timing->cl - pdram_timing->cwl;
1278 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16);
1280 tmp = get_pi_rdlat_adj(pdram_timing);
1281 mmio_clrsetbits_32(PI_REG(i, 89), 0xffu << 24, tmp << 24);
1283 tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
1284 mmio_clrsetbits_32(PI_REG(i, 90), 0xffu << 24, tmp << 24);
1286 tmp1 = tmp;
1288 tmp = 0;
1290 tmp = tmp1 - 1;
1292 tmp = tmp1 - 5;
1293 mmio_clrsetbits_32(PI_REG(i, 91), 0xffu << 24, tmp << 24);
1299 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5;
1300 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff << 16, tmp << 16);
1302 tmp = tmp + 18;
1303 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff, tmp);
1312 tmp = tmp1 + 5;
1314 tmp << 16);
1316 tmp = 10000 / (1000000 / pdram_timing->mhz);
1318 tmp++;
1320 tmp = tmp + 1;
1322 tmp = tmp + 8;
1324 tmp << 24);
1505 uint32_t tmp, i, div, j;
1528 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3;
1530 tmp++;
1531 mmio_clrsetbits_32(PHY_REG(i, 87), 0xf << 16, tmp << 16);
1532 mmio_clrsetbits_32(PHY_REG(i, 215), 0xf << 16, tmp << 16);
1533 mmio_clrsetbits_32(PHY_REG(i, 343), 0xf << 16, tmp << 16);
1534 mmio_clrsetbits_32(PHY_REG(i, 471), 0xf << 16, tmp << 16);
1540 tmp = (1 << 12) | (2 << 7) | (1 << 1);
1541 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp);
1542 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp);
1548 tmp = (2 << 7) | (1 << 5) | (1 << 1);
1549 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16);
1550 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16);
1555 tmp = 1;
1557 tmp = 3;
1559 tmp = 4;
1561 tmp = 5;
1562 mmio_clrsetbits_32(PHY_REG(i, 922), 0xf << 24, tmp << 24);
1565 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) {
1569 mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8);
1589 tmp = gate_delay_frac_ps * 0x200 / 1000;
1592 mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16);
1593 mmio_clrsetbits_32(PHY_REG(i, 205), 0x2ff << 16, tmp << 16);
1594 mmio_clrsetbits_32(PHY_REG(i, 333), 0x2ff << 16, tmp << 16);
1595 mmio_clrsetbits_32(PHY_REG(i, 461), 0x2ff << 16, tmp << 16);
1597 tmp = gate_delay_ps / 1000;
1600 mmio_clrsetbits_32(PHY_REG(i, 10), 0xf, tmp);
1601 mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp);
1602 mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp);
1603 mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp);
1606 tmp = rddqs_delay_ps / (1000000 / pdram_timing->mhz) + 2;
1607 mmio_clrsetbits_32(PHY_REG(i, 80), 0xf << 16, tmp << 16);
1608 mmio_clrsetbits_32(PHY_REG(i, 208), 0xf << 16, tmp << 16);
1609 mmio_clrsetbits_32(PHY_REG(i, 336), 0xf << 16, tmp << 16);
1610 mmio_clrsetbits_32(PHY_REG(i, 464), 0xf << 16, tmp << 16);
1630 tmp = 0;
1632 tmp = rddata_en_ie_dly - 0 - extra_adder;
1634 tmp = extra_adder;
1637 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 16, tmp << 16);
1638 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 16, tmp << 16);
1639 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 16, tmp << 16);
1640 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 16, tmp << 16);
1643 mmio_clrsetbits_32(PHY_REG(i, 86), 0xf, tmp);
1644 mmio_clrsetbits_32(PHY_REG(i, 214), 0xf, tmp);
1645 mmio_clrsetbits_32(PHY_REG(i, 342), 0xf, tmp);
1646 mmio_clrsetbits_32(PHY_REG(i, 470), 0xf, tmp);
1653 tmp = tsel_adder;
1655 tmp = rddata_en_ie_dly - 0 + extra_adder;
1658 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 8, tmp << 8);
1659 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 8, tmp << 8);
1660 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 8, tmp << 8);
1661 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 8, tmp << 8);
1664 mmio_clrsetbits_32(PHY_REG(i, 85), 0xf << 24, tmp << 24);
1665 mmio_clrsetbits_32(PHY_REG(i, 213), 0xf << 24, tmp << 24);
1666 mmio_clrsetbits_32(PHY_REG(i, 341), 0xf << 24, tmp << 24);
1667 mmio_clrsetbits_32(PHY_REG(i, 469), 0xf << 24, tmp << 24);
1743 uint32_t tmp, i;
1755 tmp = i ? 12 : 8;
1756 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) &
1758 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp);
1781 uint32_t tmp, i, val;
1790 tmp = i ? 12 : 8;
1792 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp);
1805 uint32_t tmp, i;
1810 tmp = (2 << 16) | (0x7 << 8);
1812 tmp = (3 << 16) | (0x7 << 8);
1815 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp);