Lines Matching defs:timing_config
44 struct timing_related_config timing_config;
361 struct timing_related_config *timing_config)
365 if (timing_config->dram_type == LPDDR3) {
387 struct timing_related_config *timing_config)
389 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1;
393 struct timing_related_config *timing_config)
421 if (timing_config->dram_type == DDR3) {
423 } else if (timing_config->dram_type == LPDDR4) {
425 } else if (timing_config->dram_type == LPDDR3) {
450 struct timing_related_config *timing_config)
454 if (timing_config->dram_type == LPDDR3)
456 else if (timing_config->dram_type == LPDDR4)
468 struct timing_related_config *timing_config)
472 if ((timing_config->dram_type == LPDDR4)
473 || (timing_config->dram_type == LPDDR3))
486 *timing_config,
492 for (i = 0; i < timing_config->ch_cnt; i++) {
493 if (timing_config->dram_type == DDR3) {
494 tmp = ((700000 + 10) * timing_config->freq +
510 } else if (timing_config->dram_type == LPDDR4) {
589 (timing_config->dllbp << 24));
615 if (timing_config->dram_type == LPDDR4) {
638 if (timing_config->odt) {
640 if (timing_config->freq < 400)
654 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl)
655 << 8) | get_rdlat_adj(timing_config->dram_type,
664 if ((timing_config->dram_type == LPDDR3) ||
665 (timing_config->dram_type == LPDDR4)) {
666 tmp = get_pi_wrlat(pdram_timing, timing_config);
667 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
675 if ((timing_config->dram_type == LPDDR3) ||
676 (timing_config->dram_type == LPDDR4)) {
679 get_pi_todtoff_min(pdram_timing, timing_config) - 1;
681 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
691 timing_config) &
714 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config);
715 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) {
728 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) &&
738 *timing_config,
744 for (i = 0; i < timing_config->ch_cnt; i++) {
745 if (timing_config->dram_type == DDR3) {
747 ((700000 + 10) * timing_config->freq + 999) / 1000;
760 } else if (timing_config->dram_type == LPDDR4) {
839 (timing_config->dllbp << 25));
862 if (timing_config->dram_type == LPDDR4) {
887 if (timing_config->odt) {
889 if (timing_config->freq < 400)
902 (get_wrlat_adj(timing_config->dram_type,
904 get_rdlat_adj(timing_config->dram_type,
913 if ((timing_config->dram_type == LPDDR3) ||
914 (timing_config->dram_type == LPDDR4)) {
915 tmp = get_pi_wrlat(pdram_timing, timing_config);
916 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
924 if ((timing_config->dram_type == LPDDR3) ||
925 (timing_config->dram_type == LPDDR4)) {
928 get_pi_todtoff_min(pdram_timing, timing_config);
931 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
941 timing_config) &
964 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config);
965 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) {
979 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) &&
1015 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config,
1020 gen_rk3399_ctl_params_f0(timing_config, pdram_timing);
1022 gen_rk3399_ctl_params_f1(timing_config, pdram_timing);
1025 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
1031 for (i = 0; i < timing_config->ch_cnt; i++) {
1042 if (timing_config->dram_type == LPDDR4)
1048 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config);
1051 if (timing_config->dram_type == LPDDR3) {
1052 tmp = get_pi_wrlat(pdram_timing, timing_config);
1068 if (timing_config->dram_type == LPDDR3) {
1069 tmp = get_pi_todtoff_max(pdram_timing, timing_config);
1074 if ((timing_config->dram_type == LPDDR3) ||
1075 (timing_config->dram_type == LPDDR4)) {
1076 tmp1 = get_pi_wrlat(pdram_timing, timing_config);
1077 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1082 } else if (timing_config->dram_type == DDR3) {
1087 if ((timing_config->dram_type == LPDDR3) ||
1088 (timing_config->dram_type == LPDDR4)) {
1091 tmp1 += get_pi_todtoff_min(pdram_timing, timing_config);
1094 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1099 } else if (timing_config->dram_type == DDR3) {
1107 tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
1203 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
1209 for (i = 0; i < timing_config->ch_cnt; i++) {
1220 if (timing_config->dram_type == LPDDR4)
1226 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config);
1229 if (timing_config->dram_type == LPDDR3) {
1230 tmp = get_pi_wrlat(pdram_timing, timing_config);
1245 if (timing_config->dram_type == LPDDR3) {
1246 tmp = get_pi_todtoff_max(pdram_timing, timing_config);
1250 if ((timing_config->dram_type == LPDDR3) ||
1251 (timing_config->dram_type == LPDDR4)) {
1252 tmp1 = get_pi_wrlat(pdram_timing, timing_config);
1253 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1258 } else if (timing_config->dram_type == DDR3) {
1263 if ((timing_config->dram_type == LPDDR3) ||
1264 (timing_config->dram_type == LPDDR4)) {
1267 get_pi_todtoff_min(pdram_timing, timing_config);
1270 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1275 } else if (timing_config->dram_type == DDR3)
1283 tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
1383 static void gen_rk3399_pi_params(struct timing_related_config *timing_config,
1388 gen_rk3399_pi_params_f0(timing_config, pdram_timing);
1390 gen_rk3399_pi_params_f1(timing_config, pdram_timing);
1398 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) {
1500 static void gen_rk3399_phy_params(struct timing_related_config *timing_config,
1511 for (i = 0; i < timing_config->ch_cnt; i++) {
1521 if (timing_config->freq > 400)
1571 if (timing_config->dram_type == DDR3) {
1574 } else if (timing_config->dram_type == LPDDR4) {
1577 } else if (timing_config->dram_type == LPDDR3) {
1689 timing_config->dram_type);
1806 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt;
1807 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type;
1842 sdram_timing_cfg_init(&rk3399_dram_status.timing_config,
1853 if (rk3399_dram_status.timing_config.dram_type == DDR3) {
1921 dram_type = rk3399_dram_status.timing_config.dram_type;
1922 ch_count = rk3399_dram_status.timing_config.ch_cnt;
1930 rk3399_dram_status.timing_config.odt = arg2 & 0x1;
1947 if (rk3399_dram_status.timing_config.ch_cnt == 2)
1985 rk3399_dram_status.timing_config.freq = mhz;
1988 rk3399_dram_status.timing_config.dllbp = 1;
1990 rk3399_dram_status.timing_config.dllbp = 0;
1992 if (rk3399_dram_status.timing_config.odt == 1)
2001 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing);
2002 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config,
2004 gen_rk3399_pi_params(&rk3399_dram_status.timing_config,
2006 gen_rk3399_phy_params(&rk3399_dram_status.timing_config,
2027 gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt,
2041 if (rk3399_dram_status.timing_config.odt == 0)
2048 gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt);
2075 rk3399_suspend_status.odt = rk3399_dram_status.timing_config.odt;
2077 rk3399_dram_status.timing_config.odt = 1;
2100 rk3399_dram_status.timing_config.odt = rk3399_suspend_status.odt;
2112 gen_rk3399_set_odt(rk3399_dram_status.timing_config.odt);