Lines Matching defs:rk3399_dram_status

39 struct rk3399_dram_status {
54 static struct rk3399_dram_status rk3399_dram_status;
1398 	for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) {
1806 	uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt;
1807 	uint32_t dram_type = rk3399_dram_status.timing_config.dram_type;
1841 			     &rk3399_dram_status.drv_odt_lp_cfg);
1842 	sdram_timing_cfg_init(&rk3399_dram_status.timing_config,
1844 			      &rk3399_dram_status.drv_odt_lp_cfg);
1849 	rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39;
1850 	rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39;
1851 	rk3399_dram_status.current_index =
1853 	if (rk3399_dram_status.timing_config.dram_type == DDR3) {
1854 		rk3399_dram_status.index_freq[0] /= 2;
1855 		rk3399_dram_status.index_freq[1] /= 2;
1858 		rk3399_dram_status.index_freq[rk3399_dram_status.current_index];
1860 	rk3399_dram_status.boot_freq = boot_freq;
1861 	rk3399_dram_status.index_freq[rk3399_dram_status.current_index] =
1863 	rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) &
1865 	rk3399_dram_status.low_power_stat = 0;
1897 				   rk3399_dram_status.current_index << 8);
1917 	struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg;
1918 	uint32_t *low_power = &rk3399_dram_status.low_power_stat;
1921 	dram_type = rk3399_dram_status.timing_config.dram_type;
1922 	ch_count = rk3399_dram_status.timing_config.ch_cnt;
1930 	rk3399_dram_status.timing_config.odt = arg2 & 0x1;
1947 		if (rk3399_dram_status.timing_config.ch_cnt == 2)
1985 	rk3399_dram_status.timing_config.freq = mhz;
1988 		rk3399_dram_status.timing_config.dllbp = 1;
1990 		rk3399_dram_status.timing_config.dllbp = 0;
1992 	if (rk3399_dram_status.timing_config.odt == 1)
1995 	index = (rk3399_dram_status.current_index + 1) & 0x1;
2001 	dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing);
2002 	gen_rk3399_ctl_params(&rk3399_dram_status.timing_config,
2004 	gen_rk3399_pi_params(&rk3399_dram_status.timing_config,
2006 	gen_rk3399_phy_params(&rk3399_dram_status.timing_config,
2007 			      &rk3399_dram_status.drv_odt_lp_cfg,
2009 	rk3399_dram_status.index_freq[index] = mhz;
2020 	    rk3399_dram_status.index_freq[rk3399_dram_status.current_index])
2027 	gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt,
2041 	if (rk3399_dram_status.timing_config.odt == 0)
2044 	rk3399_dram_status.current_index = ddr_index;
2045 	low_power = rk3399_dram_status.low_power_stat;
2048 	gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt);
2065 		rk3399_dram_status.index_freq[rk3399_dram_status.current_index];
2074 		rk3399_dram_status.low_power_stat;
2075 	rk3399_suspend_status.odt = rk3399_dram_status.timing_config.odt;
2076 	rk3399_dram_status.low_power_stat = 0;
2077 	rk3399_dram_status.timing_config.odt = 1;
2078 	if (mhz != rk3399_dram_status.boot_freq)
2079 		ddr_set_rate(rk3399_dram_status.boot_freq * 1000 * 1000);
2086 	prepare_ddr_timing(rk3399_dram_status.boot_freq);
2096 	rk3399_dram_status.current_index =
2098 	rk3399_dram_status.low_power_stat =
2100 	rk3399_dram_status.timing_config.odt = rk3399_suspend_status.odt;
2107 	    rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) {
2112 	gen_rk3399_set_odt(rk3399_dram_status.timing_config.odt);
2113 	resume_low_power(rk3399_dram_status.low_power_stat);