Lines Matching defs:pdram_timing
318 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing)
327 rdlat = pdram_timing->cl + PI_ADD_LATENCY;
328 delay_adder = ie_enable / (1000000 / pdram_timing->mhz);
329 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
335 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz);
336 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0)
360 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing,
366 tmp = pdram_timing->cl;
386 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing,
389 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1;
392 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing,
402 delay_adder = ie_enable / (1000000 / pdram_timing->mhz);
403 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
411 cas_lat = pdram_timing->cl + PI_ADD_LATENCY;
416 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz);
417 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
432 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz);
433 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0)
437 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz);
438 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0)
449 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing,
461 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz);
462 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0)
467 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing,
479 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz);
480 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0)
487 struct dram_timing_t *pdram_timing)
496 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) +
497 pdram_timing->tmod + pdram_timing->tzqinit;
501 pdram_timing->tdllk);
504 (pdram_timing->tmod << 8) |
505 pdram_timing->tmrd);
508 (pdram_timing->txsr -
509 pdram_timing->trcd) << 16);
511 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 +
512 pdram_timing->tinit3);
514 (pdram_timing->tmrd << 8) |
515 pdram_timing->tmrd);
517 pdram_timing->txsr << 16);
519 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1);
520 mmio_write_32(CTL_REG(i, 7), pdram_timing->tinit4);
522 (pdram_timing->tmrd << 8) |
523 pdram_timing->tmrd);
525 pdram_timing->txsr << 16);
527 mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3);
528 mmio_write_32(CTL_REG(i, 8), pdram_timing->tinit5);
530 ((pdram_timing->cl * 2) << 16));
532 (pdram_timing->cwl << 24));
533 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al);
535 (pdram_timing->trc << 24) |
536 (pdram_timing->trrd << 16));
538 (pdram_timing->tfaw << 24) |
539 (pdram_timing->trppb << 16) |
540 (pdram_timing->twtr << 8) |
541 pdram_timing->tras_min);
544 max(4, pdram_timing->trtp) << 24);
545 mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) |
546 pdram_timing->tras_max);
548 max(1, pdram_timing->tckesr));
551 (pdram_timing->twr << 16) |
552 (pdram_timing->trcd << 8));
554 pdram_timing->tmrz << 16);
555 tmp = pdram_timing->tdal ? pdram_timing->tdal :
556 (pdram_timing->twr + pdram_timing->trp);
558 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp);
560 ((pdram_timing->trefi - 8) << 16) |
561 pdram_timing->trfc);
562 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp);
564 pdram_timing->txpdll << 16);
566 pdram_timing->tcscke << 24);
567 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri);
569 (pdram_timing->tzqcke << 24) |
570 (pdram_timing->tmrwckel << 16) |
571 (pdram_timing->tckehcs << 8) |
572 pdram_timing->tckelcs);
573 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr);
575 (pdram_timing->tckehcmd << 24) |
576 (pdram_timing->tckelcmd << 16));
578 (pdram_timing->tckelpd << 24) |
579 (pdram_timing->tescke << 16) |
580 (pdram_timing->tsr << 8) |
581 pdram_timing->tckckel);
583 (pdram_timing->tcmdcke << 8) |
584 pdram_timing->tcsckeh);
586 (pdram_timing->tcksrx << 16) |
587 (pdram_timing->tcksre << 8));
591 (pdram_timing->tvrcg_enable << 16));
592 mmio_write_32(CTL_REG(i, 123), (pdram_timing->tfc_long << 16) |
593 pdram_timing->tvrcg_disable);
595 (pdram_timing->tvref_long << 16) |
596 (pdram_timing->tckfspx << 8) |
597 pdram_timing->tckfspe);
598 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) |
599 pdram_timing->mr[0]);
601 pdram_timing->mr[2]);
603 pdram_timing->mr[3]);
605 pdram_timing->mr11 << 24);
607 (pdram_timing->mr[1] << 16) |
608 pdram_timing->mr[0]);
610 pdram_timing->mr[2]);
612 pdram_timing->mr[3]);
614 pdram_timing->mr11 << 24);
617 pdram_timing->mr12 << 16);
619 pdram_timing->mr14 << 16);
621 pdram_timing->mr22 << 16);
623 pdram_timing->mr12 << 16);
625 pdram_timing->mr14 << 16);
627 pdram_timing->mr22 << 16);
630 pdram_timing->tzqinit << 8);
631 mmio_write_32(CTL_REG(i, 180), (pdram_timing->tzqcs << 16) |
632 (pdram_timing->tzqinit / 2));
633 mmio_write_32(CTL_REG(i, 181), (pdram_timing->tzqlat << 16) |
634 pdram_timing->tzqcal);
636 pdram_timing->todton << 8);
651 (pdram_timing->tdqsck << 16) |
652 (pdram_timing->tdqsck_max << 8));
654 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl)
656 pdram_timing->cl);
659 (4 * pdram_timing->trefi) << 16);
662 (2 * pdram_timing->trefi) & 0xffff);
666 tmp = get_pi_wrlat(pdram_timing, timing_config);
667 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
678 tmp = pdram_timing->cl +
679 get_pi_todtoff_min(pdram_timing, timing_config) - 1;
681 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
684 tmp = pdram_timing->cl - pdram_timing->cwl;
690 (get_pi_tdfi_phy_rdlat(pdram_timing,
695 (2 * pdram_timing->trefi) & 0xffff);
698 (2 * pdram_timing->trefi) & 0xffff);
700 mmio_write_32(CTL_REG(i, 283), 20 * pdram_timing->trefi);
703 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
704 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
714 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config);
729 (pdram_timing->cl >= 5))
730 tmp = pdram_timing->cl - 5;
732 tmp = pdram_timing->cl - 2;
739 struct dram_timing_t *pdram_timing)
748 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) +
749 pdram_timing->tmod + pdram_timing->tzqinit;
752 pdram_timing->tdllk << 16);
754 (pdram_timing->tmod << 24) |
755 (pdram_timing->tmrd << 16) |
756 (pdram_timing->trtp << 8));
758 (pdram_timing->txsr -
759 pdram_timing->trcd) << 16);
761 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1 +
762 pdram_timing->tinit3);
764 (pdram_timing->tmrd << 24) |
765 (pdram_timing->tmrd << 16) |
766 (pdram_timing->trtp << 8));
768 pdram_timing->txsr << 16);
770 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1);
771 mmio_write_32(CTL_REG(i, 11), pdram_timing->tinit4);
773 (pdram_timing->tmrd << 24) |
774 (pdram_timing->tmrd << 16) |
775 (pdram_timing->trtp << 8));
777 pdram_timing->txsr << 16);
779 mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3);
780 mmio_write_32(CTL_REG(i, 12), pdram_timing->tinit5);
782 ((pdram_timing->cl * 2) << 8));
784 (pdram_timing->cwl << 16));
786 pdram_timing->al << 24);
788 (pdram_timing->tras_min << 24) |
789 (pdram_timing->trc << 16) |
790 (pdram_timing->trrd << 8));
792 (pdram_timing->tfaw << 16) |
793 (pdram_timing->trppb << 8) |
794 pdram_timing->twtr);
795 mmio_write_32(CTL_REG(i, 35), (pdram_timing->tcke << 24) |
796 pdram_timing->tras_max);
798 max(1, pdram_timing->tckesr));
800 (pdram_timing->trcd << 24));
801 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr);
803 pdram_timing->tmrz << 24);
804 tmp = pdram_timing->tdal ? pdram_timing->tdal :
805 (pdram_timing->twr + pdram_timing->trp);
808 pdram_timing->trp << 8);
810 ((pdram_timing->trefi - 8) << 16) |
811 pdram_timing->trfc);
813 pdram_timing->txp << 16);
815 pdram_timing->txpdll);
817 pdram_timing->tmrri << 8);
818 mmio_write_32(CTL_REG(i, 57), (pdram_timing->tmrwckel << 24) |
819 (pdram_timing->tckehcs << 16) |
820 (pdram_timing->tckelcs << 8) |
821 pdram_timing->tcscke);
822 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke);
823 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr);
825 (pdram_timing->tckehcmd << 24) |
826 (pdram_timing->tckelcmd << 16));
827 mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) |
828 (pdram_timing->tescke << 16) |
829 (pdram_timing->tsr << 8) |
830 pdram_timing->tckckel);
832 (pdram_timing->tcmdcke << 8) |
833 pdram_timing->tcsckeh);
835 (pdram_timing->tcksre << 24));
837 pdram_timing->tcksrx);
841 (pdram_timing->tvrcg_disable << 16) |
842 pdram_timing->tvrcg_enable);
843 mmio_write_32(CTL_REG(i, 126), (pdram_timing->tckfspx << 24) |
844 (pdram_timing->tckfspe << 16) |
845 pdram_timing->tfc_long);
847 pdram_timing->tvref_long);
849 pdram_timing->mr[0] << 16);
850 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) |
851 pdram_timing->mr[1]);
853 pdram_timing->mr[3] << 16);
854 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11);
856 pdram_timing->mr[0] << 16);
857 mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) |
858 pdram_timing->mr[1]);
860 pdram_timing->mr[3] << 16);
861 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11);
864 pdram_timing->mr12);
866 pdram_timing->mr14);
868 pdram_timing->mr22);
870 pdram_timing->mr12);
872 pdram_timing->mr14);
874 pdram_timing->mr22);
877 ((pdram_timing->tzqinit / 2) << 16) |
878 pdram_timing->tzqinit);
879 mmio_write_32(CTL_REG(i, 183), (pdram_timing->tzqcal << 16) |
880 pdram_timing->tzqcs);
881 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat);
883 pdram_timing->tzqreset);
885 pdram_timing->todton << 16);
899 (pdram_timing->tdqsck_max << 24));
900 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck);
903 pdram_timing->cwl) << 8) |
905 pdram_timing->cl));
908 (4 * pdram_timing->trefi) & 0xffff);
911 ((2 * pdram_timing->trefi) & 0xffff) << 16);
915 tmp = get_pi_wrlat(pdram_timing, timing_config);
916 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
927 tmp = pdram_timing->cl +
928 get_pi_todtoff_min(pdram_timing, timing_config);
931 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);
934 tmp = pdram_timing->cl - pdram_timing->cwl;
940 (get_pi_tdfi_phy_rdlat(pdram_timing,
945 ((2 * pdram_timing->trefi) & 0xffff) << 16);
948 (2 * pdram_timing->trefi) & 0xffff);
950 mmio_write_32(CTL_REG(i, 290), 20 * pdram_timing->trefi);
953 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
954 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
964 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config);
980 (pdram_timing->cl >= 5))
981 tmp = pdram_timing->cl - 5;
983 tmp = pdram_timing->cl - 2;
1016 struct dram_timing_t *pdram_timing,
1020 gen_rk3399_ctl_params_f0(timing_config, pdram_timing);
1022 gen_rk3399_ctl_params_f1(timing_config, pdram_timing);
1026 struct dram_timing_t *pdram_timing)
1033 tmp = 4 * pdram_timing->trefi;
1036 tmp = 2 * pdram_timing->trefi;
1046 tmp = (pdram_timing->bl / 2) + 4 +
1047 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp +
1048 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config);
1052 tmp = get_pi_wrlat(pdram_timing, timing_config);
1061 (pdram_timing->cl * 2) << 16);
1064 pdram_timing->trefi << 16);
1066 mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc);
1069 tmp = get_pi_todtoff_max(pdram_timing, timing_config);
1076 tmp1 = get_pi_wrlat(pdram_timing, timing_config);
1077 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1090 tmp1 = pdram_timing->cl;
1091 tmp1 += get_pi_todtoff_min(pdram_timing, timing_config);
1094 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1100 tmp = pdram_timing->cl - pdram_timing->cwl;
1104 tmp = get_pi_rdlat_adj(pdram_timing);
1107 tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
1119 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
1120 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
1128 pdram_timing->tmrz << 8);
1130 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz);
1131 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0)
1137 tmp = 10000 / (1000000 / pdram_timing->mhz);
1138 if ((10000 % (1000000 / pdram_timing->mhz)) != 0)
1140 if (pdram_timing->mhz <= 100)
1147 pdram_timing->mr[1] << 8);
1149 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]);
1152 pdram_timing->mr[1] << 16);
1154 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]);
1156 mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]);
1159 pdram_timing->mr[2] << 16);
1161 mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]);
1164 pdram_timing->mr[2] << 16);
1167 pdram_timing->tfc_long);
1170 pdram_timing->twr << 24);
1173 pdram_timing->twtr << 16);
1176 pdram_timing->trcd << 8);
1178 mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp);
1181 pdram_timing->trtp << 24);
1184 pdram_timing->tras_min << 24);
1186 tmp = pdram_timing->tras_max * 99 / 100;
1190 pdram_timing->tmrd << 16);
1193 pdram_timing->tdqsck_max);
1196 (2 * pdram_timing->trefi) << 8);
1199 20 * pdram_timing->trefi);
1204 struct dram_timing_t *pdram_timing)
1211 tmp = 4 * pdram_timing->trefi;
1214 tmp = 2 * pdram_timing->trefi;
1224 tmp = (pdram_timing->bl / 2) + 4 +
1225 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp +
1226 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config);
1230 tmp = get_pi_wrlat(pdram_timing, timing_config);
1238 (pdram_timing->cl * 2) << 8);
1241 pdram_timing->trefi << 16);
1243 mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc);
1246 tmp = get_pi_todtoff_max(pdram_timing, timing_config);
1252 tmp1 = get_pi_wrlat(pdram_timing, timing_config);
1253 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1266 tmp1 = pdram_timing->cl +
1267 get_pi_todtoff_min(pdram_timing, timing_config);
1270 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);
1276 tmp = pdram_timing->cl - pdram_timing->cwl;
1280 tmp = get_pi_rdlat_adj(pdram_timing);
1283 tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
1296 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
1297 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
1305 mmio_clrsetbits_32(PI_REG(i, 103), 0x1f, pdram_timing->tmrz);
1308 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz);
1309 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0)
1316 tmp = 10000 / (1000000 / pdram_timing->mhz);
1317 if ((10000 % (1000000 / pdram_timing->mhz)) != 0)
1319 if (pdram_timing->mhz <= 100)
1326 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff, pdram_timing->mr[1]);
1329 pdram_timing->mr[1] << 8);
1331 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff, pdram_timing->mr[1]);
1334 pdram_timing->mr[1] << 8);
1337 pdram_timing->mr[2] << 16);
1339 mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]);
1342 pdram_timing->mr[2] << 16);
1344 mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]);
1347 pdram_timing->tfc_long << 16);
1350 pdram_timing->twr << 8);
1352 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr);
1355 pdram_timing->trcd << 24);
1358 pdram_timing->trp << 16);
1361 pdram_timing->trtp << 8);
1364 pdram_timing->tras_min << 24);
1367 pdram_timing->tras_max * 99 / 100);
1370 pdram_timing->tmrd << 16);
1373 pdram_timing->tdqsck_max);
1376 2 * pdram_timing->trefi);
1379 20 * pdram_timing->trefi);
1384 struct dram_timing_t *pdram_timing,
1388 gen_rk3399_pi_params_f0(timing_config, pdram_timing);
1390 gen_rk3399_pi_params_f1(timing_config, pdram_timing);
1502 struct dram_timing_t *pdram_timing,
1528 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3;
1529 if ((2500 % (1000000 / pdram_timing->mhz)) != 0)
1554 if (pdram_timing->mhz <= 400)
1556 else if (pdram_timing->mhz <= 800)
1558 else if (pdram_timing->mhz <= 1000)
1564 div = pdram_timing->mhz / (2 * 20);
1586 (1000000 / pdram_timing->mhz);
1606 tmp = rddqs_delay_ps / (1000000 / pdram_timing->mhz) + 2;
1612 cas_lat = pdram_timing->cl + PI_ADD_LATENCY;
1613 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz);
1614 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
1617 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz);
1618 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0)
1669 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) {
1688 gen_rk3399_phy_dll_bypass(pdram_timing->mhz, i, fn,