Lines Matching defs:mhz
28 {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1},
29 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1},
30 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1},
31 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1},
32 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1},
33 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1},
34 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1},
35 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1},
36 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2},
328 delay_adder = ie_enable / (1000000 / pdram_timing->mhz);
329 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
335 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz);
336 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0)
402 delay_adder = ie_enable / (1000000 / pdram_timing->mhz);
403 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
416 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz);
417 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
432 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz);
433 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0)
437 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz);
438 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0)
461 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz);
462 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0)
479 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz);
480 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0)
703 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
704 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
953 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
954 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
1119 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
1120 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
1130 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz);
1131 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0)
1137 tmp = 10000 / (1000000 / pdram_timing->mhz);
1138 if ((10000 % (1000000 / pdram_timing->mhz)) != 0)
1140 if (pdram_timing->mhz <= 100)
1296 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
1297 if ((20000 % (1000000 / pdram_timing->mhz)) != 0)
1308 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz);
1309 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0)
1316 tmp = 10000 / (1000000 / pdram_timing->mhz);
1317 if ((10000 % (1000000 / pdram_timing->mhz)) != 0)
1319 if (pdram_timing->mhz <= 100)
1412 static void gen_rk3399_phy_dll_bypass(uint32_t mhz, uint32_t ch,
1426 total_delay += (55 * 10000)/mhz;
1427 rddqs_latency = total_delay * mhz / 1000000;
1428 total_delay -= rddqs_latency * 1000000 / mhz;
1429 rddqs_gate_delay = total_delay * 0x200 * mhz / 1000000;
1430 if (mhz <= PHY_DLL_BYPASS_FREQ) {
1528 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3;
1529 if ((2500 % (1000000 / pdram_timing->mhz)) != 0)
1554 if (pdram_timing->mhz <= 400)
1556 else if (pdram_timing->mhz <= 800)
1558 else if (pdram_timing->mhz <= 1000)
1564 div = pdram_timing->mhz / (2 * 20);
1586 (1000000 / pdram_timing->mhz);
1606 tmp = rddqs_delay_ps / (1000000 / pdram_timing->mhz) + 2;
1613 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz);
1614 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0)
1617 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz);
1618 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0)
1669 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) {
1688 gen_rk3399_phy_dll_bypass(pdram_timing->mhz, i, fn,
1693 static int to_get_clk_index(unsigned int mhz)
1701 if (mhz >= dpll_rates_table[i].mhz)
1705 /* if mhz lower than lowest frequency in table, use lowest frequency */
1859 boot_freq = dpll_rates_table[to_get_clk_index(boot_freq)].mhz;
1973 mmio_write_32(M0_PARAM_ADDR + PARAM_DRAM_FREQ, pll_div.mhz);
1980 static uint32_t prepare_ddr_timing(uint32_t mhz)
1985 rk3399_dram_status.timing_config.freq = mhz;
1987 if (mhz < 300)
2009 rk3399_dram_status.index_freq[index] = mhz;
2017 uint32_t mhz = hz / (1000 * 1000);
2019 if (mhz ==
2021 return mhz;
2023 index = to_get_clk_index(mhz);
2024 mhz = dpll_rates_table[index].mhz;
2026 ddr_index = prepare_ddr_timing(mhz);
2028 mhz);
2049 return mhz;
2055 uint32_t mhz = hz / (1000 * 1000);
2057 index = to_get_clk_index(mhz);
2059 return dpll_rates_table[index].mhz * 1000 * 1000;
2064 uint32_t mhz =
2071 rk3399_suspend_status.freq = mhz;
2078 if (mhz != rk3399_dram_status.boot_freq)