Lines Matching defs:cpu_id

108 static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id)
110 	assert(cpu_id < PLATFORM_CORE_COUNT);
111 	return cores_pd_cfg_info[cpu_id];
114 static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value)
116 	assert(cpu_id < PLATFORM_CORE_COUNT);
117 	cores_pd_cfg_info[cpu_id] = value;
119 	flush_dcache_range((uintptr_t)&cores_pd_cfg_info[cpu_id],
387 static int cpus_power_domain_on(uint32_t cpu_id)
391 	cpu_pd = PD_CPU0 + cpu_id;
392 	cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id);
396 		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
399 			mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
419 		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
426 static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg)
430 	cpu_pd = PD_CPU0 + cpu_id;
435 		if (check_cpu_wfie(cpu_id))
438 		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
440 		set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg);
443 		set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg);
447 		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
470 	uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
472 	assert(cpu_id < PLATFORM_CORE_COUNT);
473 	assert(cpuson_flags[cpu_id] == 0);
474 	cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG;
475 	cpuson_entry_point[cpu_id] = entrypoint;
478 	cpus_power_domain_on(cpu_id);
485 	uint32_t cpu_id = plat_my_core_pos();
487 	mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),
494 	uint32_t cpu_id = plat_my_core_pos();
496 	cpus_power_domain_off(cpu_id, core_pwr_wfi);
503 	uint32_t cpu_id = plat_my_core_pos();
505 	assert(cpu_id < PLATFORM_CORE_COUNT);
506 	assert(cpuson_flags[cpu_id] == 0);
507 	cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN;
508 	cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint();
511 	cpus_power_domain_off(cpu_id, core_pwr_wfi_int);
518 	uint32_t cpu_id = plat_my_core_pos();
521 	mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),