Lines Matching defs:plat_params
165 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
174 tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
175 (uint32_t)plat_params->tzdram_size);
178 if (plat_params->l2_ecc_parity_prot_dis != 1) {
204 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
210 if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) {
212 assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE);
221 assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base);
223 sc7entry_end = plat_params->sc7entry_fw_base +
224 plat_params->sc7entry_fw_size;
225 assert(sc7entry_end < plat_params->tzdram_base);
228 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
232 tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
233 plat_params->tzdram_size + offset);
239 ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base,
240 plat_params->sc7entry_fw_base,
241 plat_params->sc7entry_fw_size,
281 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
286 if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U)) {