Lines Matching defs:val
144 uint32_t val = 0;
149 val = tegra_se_read_32(se_dev, SE_INT_STATUS_REG_OFFSET);
150 for (timeout = 0; (SE_INT_OP_DONE(val) == SE_INT_OP_DONE_CLEAR) &&
153 val = tegra_se_read_32(se_dev, SE_INT_STATUS_REG_OFFSET);
164 val = tegra_se_read_32(se_dev, SE_STATUS_OFFSET);
165 for (timeout = 0; (val != 0U) && (timeout < TIMEOUT_100MS);
168 val = tegra_se_read_32(se_dev, SE_STATUS_OFFSET);
180 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET);
181 for (timeout = 0; ((val & (ARAHB_MST_ID_SE_MASK | ARAHB_MST_ID_SE2_MASK)) != 0U) &&
184 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET);
195 val = tegra_se_read_32(se_dev, SE_ERR_STATUS_REG_OFFSET);
196 if (val != 0U) {
197 ERROR("%s: error during SE operation! 0x%x", __func__, val);
212 uint32_t val = 0;
219 val = tegra_se_read_32(se_dev, SE_STATUS_OFFSET);
220 for (timeout = 0; (val != 0U) && (timeout < TIMEOUT_100MS); timeout++) {
222 val = tegra_se_read_32(se_dev, SE_STATUS_OFFSET);
231 val = tegra_se_read_32(se_dev, SE_INT_STATUS_REG_OFFSET);
232 tegra_se_write_32(se_dev, SE_INT_STATUS_REG_OFFSET, val);
243 uint32_t val = 0;
255 val = tegra_se_read_32(se_dev, SE_CTX_SAVE_AUTO_REG_OFFSET);
256 block_count = SE_CTX_SAVE_GET_BLK_COUNT(val);
277 val = (SE_CONFIG_ENC_ALG_RNG |
280 tegra_se_write_32(se_dev, SE_CONFIG_REG_OFFSET, val);
293 val = tegra_se_read_32(se_dev, SE_CTX_SAVE_AUTO_REG_OFFSET);
294 if (SE_CTX_SAVE_GET_BLK_COUNT(val) != blk_count_limit) {
296 __func__, blk_count_limit, val);
371 uint32_t val;
385 val = (DRBG_MODE_FORCE_INSTANTION | DRBG_SRC_ENTROPY);
387 val = (DRBG_MODE_FORCE_RESEED | DRBG_SRC_ENTROPY);
388 tegra_se_write_32(se_dev, SE_RNG_CONFIG_REG_OFFSET, val);
391 val = (SE_CONFIG_ENC_ALG_RNG |
394 tegra_se_write_32(se_dev, SE_CONFIG_REG_OFFSET, val);
410 uint32_t val;
429 val = (SE_CONFIG_ENC_ALG_RNG |
433 tegra_se_write_32(se_dev, SE_CONFIG_REG_OFFSET, val);
440 val = (SE_CRYPTO_INPUT_RANDOM |
446 tegra_se_write_32(se_dev, SE_CRYPTO_REG_OFFSET, val);
450 val = (DRBG_MODE_FORCE_INSTANTION | DRBG_SRC_LFSR);
452 val = (DRBG_MODE_FORCE_RESEED | DRBG_SRC_LFSR);
453 tegra_se_write_32(se_dev, SE_RNG_CONFIG_REG_OFFSET, val);
508 uint32_t val = 0;
524 val = SE_CTX_SAVE_SRC_STICKY_BITS |
526 tegra_se_write_32(se_dev, SE_CTX_SAVE_CONFIG_REG_OFFSET, val);
541 uint32_t val = 0;
558 val = SE_CTX_SAVE_SRC_AES_KEYTABLE |
561 tegra_se_write_32(se_dev, SE_CTX_SAVE_CONFIG_REG_OFFSET, val);
582 val = SE_CTX_SAVE_SRC_AES_KEYTABLE |
585 tegra_se_write_32(se_dev, SE_CTX_SAVE_CONFIG_REG_OFFSET, val);
602 val = SE_CTX_SAVE_SRC_AES_KEYTABLE |
605 tegra_se_write_32(se_dev, SE_CTX_SAVE_CONFIG_REG_OFFSET, val);
622 uint32_t val = 0;
649 val = SE_CTX_SAVE_SRC_RSA_KEYTABLE |
654 SE_CTX_SAVE_CONFIG_REG_OFFSET, val);
705 uint32_t val = 0;
717 val = SE_CTX_SAVE_SRC_PKA1_KEYTABLE |
723 SE_CTX_SAVE_CONFIG_REG_OFFSET, val);
758 uint32_t val;
761 val = tegra_se_read_32(se_dev, SE_SECURITY_REG_OFFSET);
762 val |= SE_SECURITY_TZ_LOCK_SOFT(SE_SECURE);
763 tegra_se_write_32(se_dev, SE_SECURITY_REG_OFFSET, val);
899 uint32_t val = 0;
910 val = mmio_read_32(TEGRA_FUSE_BASE + FUSE_JTAG_SECUREID_VALID);
911 ecid_valid = (val == ECID_VALID);
918 uint32_t val = 0;
921 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_W);
922 val |= ENTROPY_CLK_ENB_BIT;
923 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_W, val);
926 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEVICES_W);
927 val &= ~ENTROPY_RESET_BIT;
928 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEVICES_W, val);
938 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_V);
939 val |= SE_CLK_ENB_BIT;
940 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_V, val);
943 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEVICES_V);
944 val &= ~SE_RESET_BIT;
945 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEVICES_V, val);
950 uint32_t val = 0;
953 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_W);
954 val &= ~ENTROPY_CLK_ENB_BIT;
955 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_W, val);
958 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_V);
959 val &= ~SE_CLK_ENB_BIT;
960 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_V, val);
970 uint32_t val = 0;
974 val = mmio_read_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0);
975 val &= ~PPCS_SMMU_ENABLE;
976 mmio_write_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0, val);
1011 uint32_t val = 0;
1018 val = (SE_TZRAM_OP_REQ_INIT | SE_TZRAM_OP_MODE_SAVE);
1019 tegra_se_write_32(&se_dev_1, SE_TZRAM_OPERATION, val);
1021 val = tegra_se_read_32(&se_dev_1, SE_TZRAM_OPERATION);
1022 for (timeout = 0; (SE_TZRAM_OP_BUSY(val) == SE_TZRAM_OP_BUSY_ON) &&
1025 val = tegra_se_read_32(&se_dev_1, SE_TZRAM_OPERATION);
1047 uint32_t val;
1052 val = DRBG_RO_ENT_IGNORE_MEM_ENABLE |
1055 tegra_se_write_32(se_dev, SE_RNG_SRC_CONFIG_REG_OFFSET, val);