Lines Matching defs:val
55 uint32_t val = 0, timeout = 0, sha_status, aes_status;
64 val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
65 se_is_busy = ((val & CTX_SAVE_AUTO_SE_BUSY) != 0U);
101 uint32_t val = 0, timeout = 0;
106 val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
107 se_is_ready = (val == CTX_SAVE_AUTO_SE_READY);
195 uint32_t val = 0U;
198 val = tegra_se_read_32(SE0_INT_STATUS_REG_OFFSET);
199 while (SE0_INT_OP_DONE(val) == SE0_INT_OP_DONE_CLEAR) {
200 val = tegra_se_read_32(SE0_INT_STATUS_REG_OFFSET);
201 if (SE0_INT_OP_DONE(val) != SE0_INT_OP_DONE_CLEAR) {
207 val = tegra_se_read_32(SE0_SHA_STATUS_0);
208 while (val != SE0_SHA_STATUS_IDLE) {
209 val = tegra_se_read_32(SE0_SHA_STATUS_0);
210 if (val == SE0_SHA_STATUS_IDLE) {
216 val = tegra_se_read_32(SE0_ERR_STATUS_REG_OFFSET);
217 if (val != 0U) {
219 val);
232 uint32_t val = 0U;
250 val = tegra_se_read_32(SE0_INT_STATUS_REG_OFFSET);
251 if (val > 0U) {
275 uint32_t val, last_buf, i;
300 val = (uint32_t)(SE0_CONFIG_ENC_ALG_SHA | SE0_CONFIG_ENC_MODE_SHA256 |
302 tegra_se_write_32(SE0_SHA_CONFIG, val);
341 val = SE0_SHA_CONFIG_HW_INIT_HASH;
349 val = tegra_se_read_32(SE0_SHA_HASH_RESULT_0 +
352 val);
354 val = SE0_SHA_CONFIG_HW_INIT_HASH_DISABLE;
362 tegra_se_write_32(SE0_SHA_TASK_CONFIG, val);
387 uint32_t val = 0U, hash_offset = 0U, scratch_offset = 0U;
400 val = tegra_se_read_32(SE0_SHA_HASH_RESULT_0 + hash_offset);
402 val);
415 int32_t val = 0;
429 val = tegra_se_calculate_sha256_hash(src_addr, src_len_inbyte);
430 if (val != 0) {
432 return val;
441 val = tegra_se_save_sha256_pmc_scratch();
442 if (val != 0) {
446 return val;