Lines Matching defs:val
152 uint32_t val, wdata_0, wdata_1;
159 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
160 assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
171 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
172 } while ((val & wdata_0) != wdata_0);
176 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
177 } while ((val & wdata_0) != wdata_0);
179 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
180 assert(val == MC_CLIENT_HOTRESET_CTRL1_RESET_VAL);
196 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
197 } while ((val & wdata_1) != wdata_1);
201 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
202 } while ((val & wdata_1) != wdata_1);
352 val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
356 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
358 val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
361 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val);
363 val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
365 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val);
367 val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
376 val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
377 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val);
379 val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
381 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val);
388 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
389 assert(val == wdata_0);
394 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
395 assert(val == wdata_1);
405 uint32_t i, val;
418 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
419 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
421 val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
423 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
424 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
426 val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
428 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
429 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
431 val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
439 val = tegra_mc_read_32(tegra186_txn_override_cfgs[i].offset);
440 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
442 val | tegra186_txn_override_cfgs[i].cgid_tag);
607 tegra186_mc_context[0].val = (uint32_t)(ARRAY_SIZE(tegra186_mc_context)) - 1U;
614 uint32_t val;
625 val = (tegra186_streamid_sec_cfgs[i].override_enable << 16) |
628 tegra_mc_streamid_write_32(tegra186_streamid_sec_cfgs[i].offset, val);
666 uint32_t val;
688 val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK;
689 val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK;
690 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_LO, val);
692 val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK;
693 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val);