Lines Matching defs:val
22 uint64_t val = 0ULL;
36 val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
37 write_actlr_el1(val | (uint64_t)state);
51 uint64_t val = 0ULL;
57 val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) |
63 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) |
69 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) |
76 val |= CSTATE_WAKE_MASK_UPDATE_BIT;
80 val &= CSTATE_WAKE_MASK_CLEAR;
81 val |= ((uint64_t)wake_mask << CSTATE_WAKE_MASK_SHIFT);
84 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
139 uint64_t val;
149 val = ((uint64_t)stats << MCE_CSTATE_STATS_TYPE_SHIFT) | state;
158 (uint64_t)state), val);
175 uint64_t val;
191 val = ((uint64_t)wake_time << MCE_SC7_WAKE_TIME_SHIFT) |
195 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val);
235 uint32_t val;
249 val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |
253 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val);