Lines Matching defs:smmu_id
32 uint32_t val, cb_idx, smmu_id, ctx_base;
35 for (smmu_id = 0U; smmu_id < num_smmu_devices; smmu_id++) {
37 val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
40 tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
43 val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
45 tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
51 val = tegra_smmu_read_32(smmu_id,
54 tegra_smmu_write_32(smmu_id, ctx_base +
59 val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
61 tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
64 val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
66 tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
75 uint32_t cb_idx, ctx_base, smmu_id, val;
79 for (smmu_id = 0U; smmu_id < num_smmu_devices; smmu_id++) {
81 val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
83 ERROR("%s: PGSIZE_64K Mismatch - smmu_id=%d, GSR0_SECURE_ACR=%x\n",
84 __func__, smmu_id, val);
90 ERROR("%s: CACHE_LOCK Mismatch - smmu_id=%d, GSR0_SECURE_ACR=%x\n",
91 __func__, smmu_id, val);
96 val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
98 ERROR("%s: Mismatch - smmu_id=%d, GNSR_ACR=%x\n",
99 __func__, smmu_id, val);
107 val = tegra_smmu_read_32(smmu_id,
110 ERROR("%s: Mismatch - smmu_id=%d, cb_idx=%d, GSR0_PGSIZE_64K=%x\n",
111 __func__, smmu_id, cb_idx, val);