Lines Matching defs:val

47 static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val)
49 	mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val);
50 	val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]);
53 static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val)
55 	mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val);
56 	val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]);
59 static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val)
61 	mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val);
62 	val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]);
67 	uint32_t val;
69 	val = FLOWCTRL_HALT_GIC_IRQ | FLOWCTRL_HALT_GIC_FIQ |
72 	tegra_fc_halt_cpu(cpu_id, val);
74 	val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG |
76 	tegra_fc_cpu_csr(cpu_id, val | csr);
137 	uint32_t val;
148 	val = FLOWCTRL_PG_CPU_NONCPU << FLOWCTRL_ENABLE_EXT;
149 	tegra_fc_prepare_suspend(cpu, val);
158 	uint32_t val;
169 	val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT;
170 	tegra_fc_prepare_suspend(cpu, val);
179 	uint32_t val;
189 		val = mmio_read_32(flowctrl_offset_cpu_csr[i]);
190 		if ((val & FLOWCTRL_CSR_HALT_MASK) == 0U) {
204 	uint32_t val;
212 	val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT;
213 	tegra_fc_prepare_suspend(cpu, val);
233 	uint32_t val;
239 	val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG |
241 	tegra_fc_cpu_csr(cpu, val);
251 	uint32_t val;
253 	val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL);
254 	val |= FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK;
255 	tegra_fc_write_32(FLOWCTRL_BPMP_CLUSTER_CONTROL, val);
256 	val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL);
307 	uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL);
310 	tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val | FLOWCTRL_FIQ2CCPLEX_ENABLE);
318 	uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL);
321 	tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val & ~FLOWCTRL_FIQ2CCPLEX_ENABLE);