Lines Matching defs:pwrctrl
146 void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
150 1 : pwrctrl->reg_spm_apsrc_req;
152 1 : pwrctrl->reg_spm_ddr_en_req;
154 1 : pwrctrl->reg_spm_vrf18_req;
156 1 : pwrctrl->reg_spm_infra_req;
159 1 : pwrctrl->reg_spm_f26m_req;
167 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
168 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
169 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
170 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
171 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
174 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
180 ((pwrctrl->reg_wfi_op & 0x1) << 0) |
181 ((pwrctrl->reg_wfi_type & 0x1) << 1) |
182 ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
183 ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
184 ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
185 ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
186 ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
187 ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
191 ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
192 ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
193 ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
194 ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
195 ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
196 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
197 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
198 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
199 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
200 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
204 ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
205 ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
206 ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
207 ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
208 ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
209 ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
210 ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
211 ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
212 ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
213 ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
214 ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
215 ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
216 ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
217 ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
218 ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
219 ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
220 ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
221 ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
222 ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
223 ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
224 ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
225 ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
226 ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
227 ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
228 ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
229 ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
230 ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
231 ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
232 ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
233 ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29));
237 ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
238 ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
239 ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
240 ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
241 ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
242 ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
243 ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
244 ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
245 ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
246 ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
247 ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
248 ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
249 ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
250 ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
251 ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
252 ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
253 ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
254 ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
255 ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
256 ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
257 ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
258 ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
259 ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
260 ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
261 ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
262 ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
263 ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
264 ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
265 ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
266 ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
270 ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
271 ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
272 ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
273 ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
274 ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
275 ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
276 ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
277 ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
278 ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
279 ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
280 ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
281 ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
282 ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
283 ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
284 ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
285 ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
286 ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
287 ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
288 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
289 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
290 ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
291 ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
292 ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
293 ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
294 ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
295 ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
296 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
297 ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
304 ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
308 ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
318 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
329 if (pwrctrl->timer_val_cust == 0U) {
330 val = pwrctrl->timer_val;
332 val = pwrctrl->timer_val_cust;
339 if (pwrctrl->wake_src_cust == 0U) {
340 mask = pwrctrl->wake_src;
342 mask = pwrctrl->wake_src_cust;
357 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
360 if (pwrctrl->pcm_flags_cust_clr != 0U) {
361 pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
364 if (pwrctrl->pcm_flags_cust_set != 0U) {
365 pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
368 if (pwrctrl->pcm_flags1_cust_clr != 0U) {
369 pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
372 if (pwrctrl->pcm_flags1_cust_set != 0U) {
373 pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
376 mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
377 mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
378 mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
379 mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);