Lines Matching defs:MISC1_CFG_BASE
30 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040)
31 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)
32 #define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)
33 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)
34 #define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)
35 #define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)
36 #define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20)
37 #define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24)
38 #define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)
39 #define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)
40 #define DFD_INTERNAL_TEST_SO_OVER_64 (MISC1_CFG_BASE + 0x34)
41 #define DFD_INTERNAL_SW_NS_TRIGGER (MISC1_CFG_BASE + 0x3c)
42 #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)
43 #define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C)
44 #define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50)
45 #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)
46 #define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)
47 #define DFD_CLEAN_STATUS (MISC1_CFG_BASE + 0x60)
48 #define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8)
49 #define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC)
50 #define DFD_READ_ADDR (MISC1_CFG_BASE + 0x1E8)
51 #define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC)