Lines Matching defs:pwrctrl
139 void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
143 1 : pwrctrl->reg_spm_apsrc_req;
145 1 : pwrctrl->reg_spm_ddr_en_req;
147 1 : pwrctrl->reg_spm_vrf18_req;
149 1 : pwrctrl->reg_spm_infra_req;
152 1 : pwrctrl->reg_spm_f26m_req;
160 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
161 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
162 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
163 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
164 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
167 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
173 ((pwrctrl->reg_wfi_op & 0x1) << 0) |
174 ((pwrctrl->reg_wfi_type & 0x1) << 1) |
175 ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
176 ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
177 ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
178 ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
179 ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
180 ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
184 ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) |
185 ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) |
186 ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) |
187 ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) |
188 ((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4));
192 ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
193 ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
194 ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
195 ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
196 ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
197 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
198 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
199 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
200 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
201 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
205 ((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) |
206 ((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) |
207 ((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) |
208 ((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) |
209 ((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) |
210 ((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) |
211 ((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) |
212 ((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) |
213 ((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) |
214 ((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) |
215 ((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) |
216 ((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) |
217 ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) |
218 ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) |
219 ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) |
220 ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) |
221 ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) |
222 ((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) |
223 ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) |
224 ((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) |
225 ((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) |
226 ((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) |
227 ((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) |
228 ((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) |
229 ((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) |
230 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
231 ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) |
232 ((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) |
233 ((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) |
234 ((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) |
235 ((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) |
236 ((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31));
240 ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
241 ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
242 ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
243 ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
244 ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) |
245 ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
246 ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
247 ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
248 ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
249 ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) |
250 ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
251 ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
252 ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
253 ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
254 ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) |
255 ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
256 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) |
257 ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
258 ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) |
259 ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
260 ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
261 ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
262 ((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) |
263 ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
264 ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
265 ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
266 ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
267 ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) |
268 ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
269 ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
270 ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
271 ((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31));
275 ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
276 ((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) |
277 ((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) |
278 ((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) |
279 ((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) |
280 ((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) |
281 ((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) |
282 ((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) |
283 ((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) |
284 ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) |
285 ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) |
286 ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) |
287 ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) |
288 ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) |
289 ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
290 ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
291 ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
292 ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
293 ((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) |
294 ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
295 ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
296 ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
297 ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
298 ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) |
299 ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
300 ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
301 ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
302 ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
303 ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31));
307 ((pwrctrl->ccif_event_mask_b & 0xffff) << 0) |
308 ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
309 ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
310 ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
311 ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
312 ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) |
313 ((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) |
314 ((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) |
315 ((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) |
316 ((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) |
317 ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
318 ((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) |
319 ((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27));
323 ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
324 ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
325 ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) |
326 ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) |
327 ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) |
328 ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) |
329 ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) |
330 ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) |
331 ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) |
332 ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) |
333 ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) |
334 ((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27));
338 ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
342 ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
352 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
363 if (pwrctrl->timer_val_cust == 0U) {
364 val = pwrctrl->timer_val;
366 val = pwrctrl->timer_val_cust;
373 if (pwrctrl->wake_src_cust == 0U) {
374 mask = pwrctrl->wake_src;
376 mask = pwrctrl->wake_src_cust;
379 if (pwrctrl->reg_csyspwrreq_mask != 0U) {
395 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
398 if (pwrctrl->pcm_flags_cust_clr != 0U) {
399 pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
402 if (pwrctrl->pcm_flags_cust_set != 0U) {
403 pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
406 if (pwrctrl->pcm_flags1_cust_clr != 0U) {
407 pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
410 if (pwrctrl->pcm_flags1_cust_set != 0U) {
411 pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
414 mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
415 mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
416 mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
417 mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);