Lines Matching defs:i
2467 int d, i;
2471 for (i = 0; i <= reg_num; i++) {
2473 d, i, devapc_readl(
2475 d * 0x40 + i * 4)
2482 for (i = 0; i <= reg_num; i++) {
2484 d, i, devapc_readl(
2486 d * 0x40 + i * 4)
2493 for (i = 0; i <= reg_num; i++) {
2495 d, i, devapc_readl(
2497 d * 0x40 + i * 4)
2509 int d, i;
2513 for (i = 0; i <= reg_num; i++) {
2515 d, i, devapc_readl(
2517 d * 0x40 + i * 4)
2524 for (i = 0; i <= reg_num; i++) {
2526 d, i, devapc_readl(
2528 d * 0x40 + i * 4)
2535 for (i = 0; i <= reg_num; i++) {
2537 d, i, devapc_readl(
2539 d * 0x40 + i * 4)
2551 int d, i;
2555 for (i = 0; i <= reg_num; i++) {
2557 d, i, devapc_readl(
2559 d * 0x40 + i * 4)
2568 int d, i;
2572 for (i = 0; i <= reg_num; i++) {
2574 d, i, devapc_readl(
2576 d * 0x40 + i * 4)
2588 uint32_t i;
2592 for (i = 0; i < infra_ao_size; i++) {
2593 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_0,
2594 INFRA_AO_SYS0_Devices[i].d0_permission); /* APMCU */
2595 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_1,
2596 INFRA_AO_SYS0_Devices[i].d1_permission);
2597 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_2,
2598 INFRA_AO_SYS0_Devices[i].d2_permission);
2599 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_3,
2600 INFRA_AO_SYS0_Devices[i].d3_permission);
2601 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_4,
2602 INFRA_AO_SYS0_Devices[i].d4_permission);
2603 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_5,
2604 INFRA_AO_SYS0_Devices[i].d5_permission);
2605 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_6,
2606 INFRA_AO_SYS0_Devices[i].d6_permission);
2607 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_7,
2608 INFRA_AO_SYS0_Devices[i].d7_permission);
2609 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_8,
2610 INFRA_AO_SYS0_Devices[i].d8_permission);
2611 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_9,
2612 INFRA_AO_SYS0_Devices[i].d9_permission);
2613 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_10,
2614 INFRA_AO_SYS0_Devices[i].d10_permission);
2615 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_11,
2616 INFRA_AO_SYS0_Devices[i].d11_permission);
2617 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_12,
2618 INFRA_AO_SYS0_Devices[i].d12_permission);
2619 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_13,
2620 INFRA_AO_SYS0_Devices[i].d13_permission);
2621 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_14,
2622 INFRA_AO_SYS0_Devices[i].d14_permission);
2623 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_15,
2624 INFRA_AO_SYS0_Devices[i].d15_permission);
2629 for (i = 0; i < infra_ao_size; i++) {
2630 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_0,
2631 INFRA_AO_SYS1_Devices[i].d0_permission); /* APMCU */
2632 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_1,
2633 INFRA_AO_SYS1_Devices[i].d1_permission);
2634 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_2,
2635 INFRA_AO_SYS1_Devices[i].d2_permission);
2636 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_3,
2637 INFRA_AO_SYS1_Devices[i].d3_permission);
2642 for (i = 0; i < infra_ao_size; i++) {
2643 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_0,
2644 INFRA_AO_SYS2_Devices[i].d0_permission); /* APMCU */
2645 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_1,
2646 INFRA_AO_SYS2_Devices[i].d1_permission);
2647 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_2,
2648 INFRA_AO_SYS2_Devices[i].d2_permission);
2649 set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_3,
2650 INFRA_AO_SYS2_Devices[i].d3_permission);
2657 uint32_t i;
2661 for (i = 0; i < peri_ao_size; i++) {
2662 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_0,
2663 PERI_AO_SYS0_Devices[i].d0_permission); /* APMCU */
2664 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_1,
2665 PERI_AO_SYS0_Devices[i].d1_permission);
2666 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_2,
2667 PERI_AO_SYS0_Devices[i].d2_permission);
2668 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_3,
2669 PERI_AO_SYS0_Devices[i].d3_permission);
2670 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_4,
2671 PERI_AO_SYS0_Devices[i].d4_permission);
2672 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_5,
2673 PERI_AO_SYS0_Devices[i].d5_permission);
2674 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_6,
2675 PERI_AO_SYS0_Devices[i].d6_permission);
2676 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_7,
2677 PERI_AO_SYS0_Devices[i].d7_permission);
2678 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_8,
2679 PERI_AO_SYS0_Devices[i].d8_permission);
2680 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_9,
2681 PERI_AO_SYS0_Devices[i].d9_permission);
2682 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_10,
2683 PERI_AO_SYS0_Devices[i].d10_permission);
2684 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_11,
2685 PERI_AO_SYS0_Devices[i].d11_permission);
2686 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_12,
2687 PERI_AO_SYS0_Devices[i].d12_permission);
2688 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_13,
2689 PERI_AO_SYS0_Devices[i].d13_permission);
2690 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_14,
2691 PERI_AO_SYS0_Devices[i].d14_permission);
2692 set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_15,
2693 PERI_AO_SYS0_Devices[i].d15_permission);
2698 for (i = 0; i < peri_ao_size; i++) {
2699 set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_0,
2700 PERI_AO_SYS1_Devices[i].d0_permission); /* APMCU */
2701 set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_1,
2702 PERI_AO_SYS1_Devices[i].d1_permission);
2703 set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_2,
2704 PERI_AO_SYS1_Devices[i].d2_permission);
2705 set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_3,
2706 PERI_AO_SYS1_Devices[i].d3_permission);
2707 set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_4,
2708 PERI_AO_SYS1_Devices[i].d4_permission);
2709 set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_5,
2710 PERI_AO_SYS1_Devices[i].d5_permission);
2711 set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_6,
2712 PERI_AO_SYS1_Devices[i].d6_permission);
2713 set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_7,
2714 PERI_AO_SYS1_Devices[i].d7_permission);
2719 for (i = 0; i < peri_ao_size; i++) {
2720 set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_0,
2721 PERI_AO_SYS2_Devices[i].d0_permission); /* APMCU */
2722 set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_1,
2723 PERI_AO_SYS2_Devices[i].d1_permission);
2724 set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_2,
2725 PERI_AO_SYS2_Devices[i].d2_permission);
2726 set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_3,
2727 PERI_AO_SYS2_Devices[i].d3_permission);
2734 uint32_t i;
2738 for (i = 0; i < peri_ao2_size; i++) {
2739 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_0,
2740 PERI_AO2_SYS0_Devices[i].d0_permission); /* APMCU */
2741 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_1,
2742 PERI_AO2_SYS0_Devices[i].d1_permission);
2743 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_2,
2744 PERI_AO2_SYS0_Devices[i].d2_permission);
2745 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_3,
2746 PERI_AO2_SYS0_Devices[i].d3_permission);
2747 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_4,
2748 PERI_AO2_SYS0_Devices[i].d4_permission);
2749 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_5,
2750 PERI_AO2_SYS0_Devices[i].d5_permission);
2751 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_6,
2752 PERI_AO2_SYS0_Devices[i].d6_permission);
2753 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_7,
2754 PERI_AO2_SYS0_Devices[i].d7_permission);
2755 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_8,
2756 PERI_AO2_SYS0_Devices[i].d8_permission);
2757 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_9,
2758 PERI_AO2_SYS0_Devices[i].d9_permission);
2759 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_10,
2760 PERI_AO2_SYS0_Devices[i].d10_permission);
2761 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_11,
2762 PERI_AO2_SYS0_Devices[i].d11_permission);
2763 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_12,
2764 PERI_AO2_SYS0_Devices[i].d12_permission);
2765 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_13,
2766 PERI_AO2_SYS0_Devices[i].d13_permission);
2767 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_14,
2768 PERI_AO2_SYS0_Devices[i].d14_permission);
2769 set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_15,
2770 PERI_AO2_SYS0_Devices[i].d15_permission);
2777 uint32_t i;
2781 for (i = 0; i < peri_par_ao_size; i++) {
2782 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_0,
2783 PERI_PAR_AO_SYS0_Devices[i].d0_permission); /* APMCU */
2784 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_1,
2785 PERI_PAR_AO_SYS0_Devices[i].d1_permission);
2786 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_2,
2787 PERI_PAR_AO_SYS0_Devices[i].d2_permission);
2788 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_3,
2789 PERI_PAR_AO_SYS0_Devices[i].d3_permission);
2790 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_4,
2791 PERI_PAR_AO_SYS0_Devices[i].d4_permission);
2792 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_5,
2793 PERI_PAR_AO_SYS0_Devices[i].d5_permission);
2794 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_6,
2795 PERI_PAR_AO_SYS0_Devices[i].d6_permission);
2796 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_7,
2797 PERI_PAR_AO_SYS0_Devices[i].d7_permission);
2798 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_8,
2799 PERI_PAR_AO_SYS0_Devices[i].d8_permission);
2800 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_9,
2801 PERI_PAR_AO_SYS0_Devices[i].d9_permission);
2802 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_10,
2803 PERI_PAR_AO_SYS0_Devices[i].d10_permission);
2804 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_11,
2805 PERI_PAR_AO_SYS0_Devices[i].d11_permission);
2806 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_12,
2807 PERI_PAR_AO_SYS0_Devices[i].d12_permission);
2808 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_13,
2809 PERI_PAR_AO_SYS0_Devices[i].d13_permission);
2810 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_14,
2811 PERI_PAR_AO_SYS0_Devices[i].d14_permission);
2812 set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_15,
2813 PERI_PAR_AO_SYS0_Devices[i].d15_permission);