Lines Matching defs:pwrctrl
131 void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
135 1 : pwrctrl->reg_spm_apsrc_req;
137 1 : pwrctrl->reg_spm_ddren_req;
139 1 : pwrctrl->reg_spm_vrf18_req;
141 1 : pwrctrl->reg_spm_infra_req;
143 1 : pwrctrl->reg_spm_f26m_req;
150 (pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)
151 ? 0U : pwrctrl->reg_sspm_srcclkena_mask_b;
154 (pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)
155 ? 0 : pwrctrl->reg_sspm_infra_req_mask_b;
164 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
165 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
166 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
167 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
168 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
172 ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
173 ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
174 ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
175 ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
176 ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
177 ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
178 ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
179 ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
180 ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
181 ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
182 ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
183 ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
184 ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
185 ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
186 ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
187 ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
188 ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
189 ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
190 ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
191 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
192 ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
195 ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
196 ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
197 ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
200 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
206 ((pwrctrl->reg_wfi_op & 0x1) << 0) |
207 ((pwrctrl->reg_wfi_type & 0x1) << 1) |
208 ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
209 ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
210 ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
211 ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
212 ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
213 ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
217 ((pwrctrl->reg_ccif_event_infra_req_mask_b & 0xffff) << 0) |
218 ((pwrctrl->reg_ccif_event_apsrc_req_mask_b & 0xffff) << 16));
222 ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
223 ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
224 ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
225 ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
226 ((pwrctrl->reg_spm_ddren_req & 0x1) << 7) |
227 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
228 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
229 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
230 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
231 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
235 ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
236 ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
237 ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
238 ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
239 ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
240 ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
241 ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
242 ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
243 ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
244 ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
245 ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
246 ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
247 ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
248 ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
249 ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
250 ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
251 ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
252 ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
253 ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
254 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
255 ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
256 ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 27) |
257 ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 28) |
258 ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
259 ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
260 ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
264 ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
265 ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
266 ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
267 ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
268 ((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 4) |
269 ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
270 ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
271 ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
272 ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
273 ((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 9) |
274 ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
275 ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
276 ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
277 ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
278 ((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 14) |
279 ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
280 ((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 16) |
281 ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
282 ((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 18) |
283 ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
284 ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
285 ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
286 ((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 22) |
287 ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
288 ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
289 ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
290 ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
291 ((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 27) |
292 ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
293 ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
294 ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
295 ((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 31));
299 ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
300 ((pwrctrl->reg_sw2spm_wakeup_mask_b & 0xf) << 1) |
301 ((pwrctrl->reg_adsp2spm_wakeup_mask_b & 0x1) << 5) |
302 ((pwrctrl->reg_sspm2spm_wakeup_mask_b & 0xf) << 6) |
303 ((pwrctrl->reg_scp2spm_wakeup_mask_b & 0x1) << 10) |
304 ((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 11) |
305 ((pwrctrl->reg_spm_reserved_srcclkena_mask_b & 0x1) << 12) |
306 ((pwrctrl->reg_spm_reserved_infra_req_mask_b & 0x1) << 13) |
307 ((pwrctrl->reg_spm_reserved_apsrc_req_mask_b & 0x1) << 14) |
308 ((pwrctrl->reg_spm_reserved_vrf18_req_mask_b & 0x1) << 15) |
309 ((pwrctrl->reg_spm_reserved_ddren_req_mask_b & 0x1) << 16) |
310 ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
311 ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
312 ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
313 ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
314 ((pwrctrl->reg_mcupm_ddren_req_mask_b & 0x1) << 21) |
315 ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
316 ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
317 ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
318 ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
319 ((pwrctrl->reg_msdc0_ddren_req_mask_b & 0x1) << 26) |
320 ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
321 ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
322 ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
323 ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
324 ((pwrctrl->reg_msdc1_ddren_req_mask_b & 0x1) << 31));
328 ((pwrctrl->reg_ccif_event_srcclkena_mask_b & 0xffff) << 0) |
329 ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
330 ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
331 ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
332 ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
333 ((pwrctrl->reg_bak_psri_ddren_req_mask_b & 0x1) << 20) |
334 ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 21) |
335 ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 23) |
336 ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
337 ((pwrctrl->reg_dramc_md32_apsrc_req_mask_b & 0x3) << 26));
341 ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
342 ((pwrctrl->reg_mcusys_merge_ddren_req_mask_b & 0x1ff) << 9) |
343 ((pwrctrl->reg_afe_srcclkena_mask_b & 0x1) << 18) |
344 ((pwrctrl->reg_afe_infra_req_mask_b & 0x1) << 19) |
345 ((pwrctrl->reg_afe_apsrc_req_mask_b & 0x1) << 20) |
346 ((pwrctrl->reg_afe_vrf18_req_mask_b & 0x1) << 21) |
347 ((pwrctrl->reg_afe_ddren_req_mask_b & 0x1) << 22) |
348 ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 23) |
349 ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 24) |
350 ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 25) |
351 ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 26) |
352 ((pwrctrl->reg_msdc2_ddren_req_mask_b & 0x1) << 27));
356 ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
360 ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
364 ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 0) |
365 ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 1) |
366 ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 2) |
367 ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 3) |
368 ((pwrctrl->reg_pcie_ddren_req_mask_b & 0x1) << 4) |
369 ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 5) |
370 ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 6) |
371 ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 7) |
372 ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 8) |
373 ((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9));
383 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
394 if (pwrctrl->timer_val_cust == 0U) {
395 val = pwrctrl->timer_val ? (pwrctrl->timer_val) : (PCM_TIMER_MAX);
397 val = pwrctrl->timer_val_cust;
404 if (pwrctrl->wake_src_cust == 0U) {
405 mask = pwrctrl->wake_src;
407 mask = pwrctrl->wake_src_cust;
410 if (pwrctrl->reg_csyspwrup_ack_mask != 0U) {
426 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
429 if (pwrctrl->pcm_flags_cust_clr != 0U) {
430 pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
433 if (pwrctrl->pcm_flags_cust_set != 0U) {
434 pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
437 if (pwrctrl->pcm_flags1_cust_clr != 0U) {
438 pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
441 if (pwrctrl->pcm_flags1_cust_set != 0U) {
442 pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
445 mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
447 mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
449 mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
451 mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);