Lines Matching defs:MISC1_CFG_BASE
23 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xA040)
25 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)
26 #define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)
27 #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)
28 #define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)
29 #define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)
30 #define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)
31 #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)
32 #define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C)
33 #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)
34 #define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)
35 #define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC)