Lines Matching defs:pstate

153 static void armv8_2_cpu_pwr_on_common(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
169 static void armv8_2_cpu_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
171 	if ((pstate & MT_CPUPM_PWR_DOMAIN_PERCORE_DSU) != 0) {
180 static void armv8_2_cpu_pwr_resume(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
182 	armv8_2_cpu_pwr_on_common(state, pstate);
188 static void armv8_2_cpu_pwr_suspend(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
193 	armv8_2_cpu_pwr_dwn_common(state, pstate);
196 static void armv8_2_cpu_pwr_on(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
198 	armv8_2_cpu_pwr_on_common(state, pstate);
205 static void armv8_2_cpu_pwr_off(const struct mtk_cpupm_pwrstate *state, unsigned int pstate)
210 	armv8_2_cpu_pwr_dwn_common(state, pstate);
233 	unsigned int pstate = (MT_CPUPM_PWR_DOMAIN_CORE | MT_CPUPM_PWR_DOMAIN_PERCORE_DSU);
245 	armv8_2_cpu_pwr_on(&pm_state, pstate);
248 	nb.pwr_domain = pstate;
258 	unsigned int pstate = (MT_CPUPM_PWR_DOMAIN_CORE | MT_CPUPM_PWR_DOMAIN_PERCORE_DSU);
269 	armv8_2_cpu_pwr_off(&pm_state, pstate);
272 	nb.pwr_domain = pstate;
281 	unsigned int pstate = 0;
294 	pstate = get_mediatek_pstate(CPUPM_PWR_OFF,
297 	armv8_2_cpu_pwr_suspend(&pm_state, pstate);
299 	if ((pstate & MT_CPUPM_PWR_DOMAIN_CLUSTER) != 0) {
303 	if ((pstate & MT_CPUPM_PWR_DOMAIN_MCUSYS) != 0) {
308 	nb.pwr_domain = pstate;
311 	if (IS_AFFLV_PUBEVENT(pstate)) {
319 	unsigned int pstate = 0;
332 	pstate = get_mediatek_pstate(CPUPM_PWR_ON,
335 	if ((pstate & MT_CPUPM_PWR_DOMAIN_MCUSYS) != 0) {
339 	if ((pstate & MT_CPUPM_PWR_DOMAIN_CLUSTER) != 0) {
343 	armv8_2_cpu_pwr_resume(&pm_state, pstate);
346 	nb.pwr_domain = pstate;
349 	if (IS_AFFLV_PUBEVENT(pstate)) {
358 	unsigned int pstate = psci_get_pstate_type(power_state);
367 		if (mtk_cpu_pwr.ops->pwr_state_valid(aff_lvl, pstate) != 0) {
372 	if (pstate == PSTATE_TYPE_STANDBY) {