Lines Matching defs:pwrctrl
92 void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, unsigned int resource_usage)
96 1 : pwrctrl->reg_spm_apsrc_req;
98 1 : pwrctrl->reg_spm_ddr_en_req;
100 1 : pwrctrl->reg_spm_vrf18_req;
102 1 : pwrctrl->reg_spm_infra_req;
104 1 : pwrctrl->reg_spm_f26m_req;
113 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
114 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
115 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
116 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
117 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
120 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
124 ((pwrctrl->reg_wfi_op & 0x1) << 0) |
125 ((pwrctrl->reg_wfi_type & 0x1) << 1) |
126 ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
127 ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
128 ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
129 ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
130 ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
131 ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
135 ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
136 ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
137 ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
138 ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
139 ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
140 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
141 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
142 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
143 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
144 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
148 ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
149 ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
150 ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
151 ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
152 ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
153 ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
154 ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
155 ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
156 ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
157 ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
158 ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
159 ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
160 ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
161 ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
162 ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
163 ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
164 ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
165 ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
166 ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
167 ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
168 ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
169 ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
170 ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
171 ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
172 ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
173 ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
174 ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
175 ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
176 ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
177 ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29) |
178 ((pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 30) |
179 ((pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 31));
183 ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
184 ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
185 ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
186 ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
187 ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
188 ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
189 ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
190 ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
191 ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
192 ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
193 ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
194 ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
195 ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
196 ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
197 ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
198 ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
199 ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
200 ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
201 ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
202 ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
203 ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
204 ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
205 ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
206 ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
207 ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
208 ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
209 ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
210 ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
211 ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
212 ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
216 ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
217 ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
218 ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
219 ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
220 ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
221 ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
222 ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
223 ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
224 ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
225 ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
226 ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
227 ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
228 ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
229 ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
230 ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
231 ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
232 ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
233 ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
234 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
235 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
236 ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
237 ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
238 ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
239 ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
240 ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
241 ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
242 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
243 ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
247 ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
248 ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
249 ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 18) |
250 ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 20) |
251 ((pwrctrl->reg_dramc_md32_ddr_en_mask_b & 0x3) << 22) |
252 ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 24));
256 ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
260 ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
263 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
272 if (pwrctrl->timer_val_cust == 0U) {
273 val = (pwrctrl->timer_val != 0U) ? pwrctrl->timer_val : PCM_TIMER_MAX;
275 val = pwrctrl->timer_val_cust;
282 if (pwrctrl->wake_src_cust == 0U) {
283 mask = pwrctrl->wake_src;
285 mask = pwrctrl->wake_src_cust;
299 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
302 if (pwrctrl->pcm_flags_cust_clr != 0U) {
303 pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
305 if (pwrctrl->pcm_flags_cust_set != 0U) {
306 pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
308 if (pwrctrl->pcm_flags1_cust_clr != 0U) {
309 pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
311 if (pwrctrl->pcm_flags1_cust_set != 0U) {
312 pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
315 mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
317 mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
319 mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
321 mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);