Lines Matching defs:cpu_id

90 #define PWRC_CPUN_CR_REG(cpu_id)		\
91 			(MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10))
100 #define CCU_B_PRCRN_REG(cpu_id)			\
102 			((cpu_id / 2) * (0x400)) + ((cpu_id % 2) * 4))
119 static int plat_marvell_cpu_powerdown(int cpu_id)
124 	INFO("Powering down CPU%d\n", cpu_id);
127 	reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
129 	mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);
133 		reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
139 	reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
141 	mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);
146 		reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
154 	reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
156 	mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);
159 	reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id));
161 	mmio_write_32(CCU_B_PRCRN_REG(cpu_id), reg_val);
166 		reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id));
173 	INFO("Successfully powered down CPU%d\n", cpu_id);
178 	ERROR("ERROR: Can't power down CPU%d\n", cpu_id);
230 	int	cpu_id = MPIDR_CPU_GET(mpidr),
235 	cpu_id = cluster * PLAT_MARVELL_CLUSTER_CORE_COUNT + cpu_id;
237 	INFO("Powering on CPU%d\n", cpu_id);
249 	reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
251 	mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);
257 	reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
259 	mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);
265 		reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
274 	reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
276 	mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);
281 		reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
287 	reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id));
289 	mmio_write_32(CCU_B_PRCRN_REG(cpu_id), reg_val);
294 		reg_val = mmio_read_32(CCU_B_PRCRN_REG(cpu_id));
302 	INFO("Successfully powered on CPU%d\n", cpu_id);
307 	ERROR("ERROR: Can't power up CPU%d\n", cpu_id);
313 	int cpu_id;
320 	cpu_id =  MPIDR_CPU_GET(mpidr);
329 	mmio_write_32(MVEBU_CCU_RVBAR(cpu_id),
333 	mmio_write_32(MVEBU_CCU_CPU_UN_RESET(cpu_id), 0x10001);