Lines Matching defs:reg_val
360 uint32_t reg_val, avs_workpoint, freq_pidi_mode;
373 reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
374 reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK;
375 mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val);
531 reg_val = mmio_read_32(AVS_EN_CTRL_REG);
532 avs_workpoint = (reg_val &
612 reg_val = mmio_read_32(AVS_EN_CTRL_REG);
614 (reg_val & AVS_VDD_LOW_LIMIT_MASK) >> AVS_LOW_VDD_LIMIT_OFFSET,
616 reg_val &= ~(AVS_VDD_LOW_LIMIT_MASK | AVS_VDD_HIGH_LIMIT_MASK);
617 reg_val |= 0x1 << AVS_ENABLE_OFFSET;
618 reg_val |= avs_workpoint << AVS_HIGH_VDD_LIMIT_OFFSET;
619 reg_val |= avs_workpoint << AVS_LOW_VDD_LIMIT_OFFSET;
620 mmio_write_32(AVS_EN_CTRL_REG, reg_val);