Lines Matching defs:data
95 uint32_t data;
102 data = mmio_read_32(S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT);
103 if ((data & S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE) == 0)
116 uint32_t data;
128 data = mmio_read_32(S10_MPFE_HMC_ADP_DDRCALSTAT);
129 if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1)
134 if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) {
143 if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) {
204 uint32_t data, dram_addr_order, ddr_conf, bank, row, col,
213 data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG1);
214 dram_addr_order = S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(data);
216 data = mmio_read_32(S10_MPFE_IOHMC_DRAMADDRW);
218 col = IOHMC_DRAMADDRW_COL_ADDR_WIDTH(data);
219 row = IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(data);
220 bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) +
221 IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(data);
234 mmio_write_32(S10_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data);
236 data = mmio_read_32(S10_MPFE_IOHMC_DRAMTIMING0);
237 rd_latency = S10_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(data);
239 data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING0);
240 act_to_act = ACT_TO_ACT(data);
241 t_rcd = ACT_TO_RDWR(data);
242 act_to_act_bank = ACT_TO_ACT_DIFF_BANK(data);
244 data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING1);
245 rd_to_wr = RD_TO_WR(data);
246 bus_rd_to_rd = RD_TO_RD_DIFF_CHIP(data);
247 bus_rd_to_wr = RD_TO_WR_DIFF_CHIP(data);
249 data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING2);
250 t_rtp = RD_TO_PCH(data);
252 data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING3);
253 wr_to_rd = CALTIMING3_WR_TO_RD(data);
254 bus_wr_to_rd = CALTIMING3_WR_TO_RD_DIFF_CHIP(data);
256 data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING4);
257 t_rp = PCH_TO_VALID(data);
259 data = mmio_read_32(S10_MPFE_HMC_ADP(HMC_ADP_DDRIOCTRL));
260 bw_ratio = ((HMC_ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 0 : 1);
262 data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG0);
263 burst_len = HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(data);
267 data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG0);
268 switch (S10_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(data)) {
300 data = mmio_read_32(S10_MPFE_HMC_ADP(HMC_ADP_DDRIOCTRL));
301 bw_ratio_extended = ((ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 1 : 0);
310 data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING9);
311 faw = S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(data);
335 uint32_t data;
338 data = mmio_read_32(S10_MPFE_HMC_ADP_DDRIOCTRL);
339 switch (S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(data)) {
354 data = mmio_read_32(S10_MPFE_IOHMC_REG_DRAMADDRW);
355 ram_addr_width = IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(data) +
356 IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(data) +
357 IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(data) +
358 IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(data) +
359 IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(data);
368 uint32_t data;
383 data = mmio_read_32(S10_MPFE_IOHMC_REG_CTRLCFG1);
384 if (data & (1 << S10_IOHMC_CTRLCFG1_ENABLE_ECC_OFST)) {