Lines Matching defs:mbox_error
618 uint32_t *ret_size, uint32_t *mbox_error)
656 *mbox_error = -status;
658 *mbox_error = -status;
716 uint32_t mbox_error = 0;
846 &len_in_resp, &mbox_error);
847 SMC_RET4(handle, status, mbox_error, x1, len_in_resp);
884 (uint32_t *) &x7, &mbox_error);
887 (uint32_t *) &x7, &mbox_error);
892 SMC_RET4(handle, status, mbox_error, x6, x7);
896 &mbox_error);
897 SMC_RET4(handle, status, mbox_error, x1, retval64);
914 &mbox_error);
915 SMC_RET2(handle, status, mbox_error);
930 status = intel_fcs_sigma_teardown(x1, &mbox_error);
931 SMC_RET2(handle, status, mbox_error);
934 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
935 SMC_RET4(handle, status, mbox_error, retval, retval2);
939 (uint32_t *) &x4, &mbox_error);
940 SMC_RET4(handle, status, mbox_error, x3, x4);
944 (uint32_t *) &x4, &mbox_error);
945 SMC_RET4(handle, status, mbox_error, x3, x4);
949 (uint32_t *) &x3, &mbox_error);
950 SMC_RET4(handle, status, mbox_error, x2, x3);
953 status = intel_fcs_create_cert_on_reload(x1, &mbox_error);
954 SMC_RET2(handle, status, mbox_error);
957 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
958 SMC_RET3(handle, status, mbox_error, retval);
961 status = intel_fcs_close_crypto_service_session(x1, &mbox_error);
962 SMC_RET2(handle, status, mbox_error);
970 (uint32_t *) &x4, &mbox_error);
971 SMC_RET4(handle, status, mbox_error, x3, x4);
975 &mbox_error);
976 SMC_RET2(handle, status, mbox_error);
980 (uint32_t *) &x4, &mbox_error);
981 SMC_RET4(handle, status, mbox_error, x3, x4);
986 x4, x5, &mbox_error);
987 SMC_RET2(handle, status, mbox_error);
994 &mbox_error);
995 SMC_RET4(handle, status, mbox_error, x5, x6);
1002 &mbox_error);
1003 SMC_RET4(handle, status, mbox_error, x5, x6);
1010 &mbox_error, &send_id);
1011 SMC_RET4(handle, status, mbox_error, x5, x6);
1018 &mbox_error, &send_id);
1019 SMC_RET4(handle, status, mbox_error, x5, x6);
1024 x4, x5, &mbox_error);
1025 SMC_RET2(handle, status, mbox_error);
1033 false, &mbox_error);
1034 SMC_RET4(handle, status, mbox_error, x5, x6);
1042 true, &mbox_error);
1043 SMC_RET4(handle, status, mbox_error, x5, x6);
1051 false, &mbox_error, &send_id);
1052 SMC_RET4(handle, status, mbox_error, x5, x6);
1060 true, &mbox_error, &send_id);
1061 SMC_RET4(handle, status, mbox_error, x5, x6);
1066 x4, x5, &mbox_error);
1067 SMC_RET2(handle, status, mbox_error);
1074 &mbox_error);
1075 SMC_RET4(handle, status, mbox_error, x5, x6);
1082 &mbox_error);
1083 SMC_RET4(handle, status, mbox_error, x5, x6);
1090 &mbox_error, &send_id);
1091 SMC_RET4(handle, status, mbox_error, x5, x6);
1098 &mbox_error, &send_id);
1099 SMC_RET4(handle, status, mbox_error, x5, x6);
1104 x4, x5, &mbox_error);
1105 SMC_RET2(handle, status, mbox_error);
1111 x4, x5, (uint32_t *) &x6, &mbox_error);
1112 SMC_RET4(handle, status, mbox_error, x5, x6);
1117 x4, x5, &mbox_error);
1118 SMC_RET2(handle, status, mbox_error);
1124 x4, x5, (uint32_t *) &x6, &mbox_error);
1125 SMC_RET4(handle, status, mbox_error, x5, x6);
1130 x4, x5, &mbox_error);
1131 SMC_RET2(handle, status, mbox_error);
1139 x7, false, &mbox_error);
1140 SMC_RET4(handle, status, mbox_error, x5, x6);
1148 x7, false, &mbox_error, &send_id);
1149 SMC_RET4(handle, status, mbox_error, x5, x6);
1157 x7, true, &mbox_error, &send_id);
1158 SMC_RET4(handle, status, mbox_error, x5, x6);
1166 x7, true, &mbox_error);
1167 SMC_RET4(handle, status, mbox_error, x5, x6);
1172 x4, x5, &mbox_error);
1173 SMC_RET2(handle, status, mbox_error);
1177 (uint32_t *) &x4, &mbox_error);
1178 SMC_RET4(handle, status, mbox_error, x3, x4);
1183 x4, x5, &mbox_error);
1184 SMC_RET2(handle, status, mbox_error);
1190 x4, x5, (uint32_t *) &x6, &mbox_error);
1191 SMC_RET4(handle, status, mbox_error, x5, x6);
1196 &mbox_error);
1197 SMC_RET2(handle, status, mbox_error);
1215 &mbox_error);
1216 SMC_RET4(handle, status, mbox_error, x1, retval64);