Lines Matching defs:core_id
62 void imx_set_cpu_boot_entry(unsigned int core_id, uint64_t boot_entry)
65 mmio_write_32(BLK_CTRL_S_BASE + CA55_RVBADDR0_L + core_id * 8, boot_entry >> 2);
70 unsigned int core_id;
72 core_id = MPIDR_AFFLVL1_VAL(mpidr);
74 imx_set_cpu_boot_entry(core_id, secure_entrypoint);
83 mmio_clrbits_32(SRC_SLICE(SRC_A55C0 + core_id) + 0x24, BIT(2) | BIT(0));
85 mmio_setbits_32(SRC_SLICE(SRC_A55C0 + core_id) + 0x24, BIT(2) | BIT(0));
87 mmio_clrbits_32(BLK_CTRL_S_BASE + CA55_CPUWAIT, BIT(core_id));
90 gpc_assert_sw_wakeup(CPU_A55C0 + core_id);
99 unsigned int core_id = MPIDR_AFFLVL1_VAL(mpidr);
106 gpc_set_cpu_mode(CPU_A55C0 + core_id, CM_MODE_RUN);
108 gpc_deassert_sw_wakeup(CPU_A55C0 + core_id);
110 gpc_select_wakeup_gic(CPU_A55C0 + core_id);
115 src_mem_lpm_en(SRC_A55P0_MEM + core_id, MEM_OFF);
117 src_mix_set_lpm(SRC_A55C0 + core_id, core_id, CM_MODE_WAIT);
119 src_authen_config(SRC_A55C0 + core_id, 1 << core_id, 0x1);
128 unsigned int core_id = MPIDR_AFFLVL1_VAL(mpidr);
139 gpc_set_irq_mask(CPU_A55C0 + core_id, i, 0xffffffff);
142 gpc_select_wakeup_raw_irq(CPU_A55C0 + core_id);
144 gpc_set_cpu_mode(CPU_A55C0 + core_id, CM_MODE_SUSPEND);
150 unsigned int core_id = MPIDR_AFFLVL1_VAL(mpidr);
155 imx_set_cpu_boot_entry(core_id, secure_entrypoint);
157 gpc_set_cpu_mode(CPU_A55C0 + core_id, CM_MODE_WAIT);
175 unsigned int core_id = MPIDR_AFFLVL1_VAL(mpidr);
186 gpc_set_cpu_mode(CPU_A55C0 + core_id, CM_MODE_RUN);