Lines Matching defs:core_id

46 static void gpc_imr_core_spin_lock(unsigned int core_id)
48 	spin_lock(&gpc_imr_lock[core_id]);
51 static void gpc_imr_core_spin_unlock(unsigned int core_id)
53 	spin_unlock(&gpc_imr_lock[core_id]);
56 static void gpc_save_imr_lpm(unsigned int core_id, unsigned int imr_idx)
58 	uint32_t reg = gpc_imr_offset[core_id] + imr_idx * 4;
60 	gpc_imr_core_spin_lock(core_id);
62 	gpc_saved_imrs[core_id + imr_idx * 4] = mmio_read_32(reg);
65 	gpc_imr_core_spin_unlock(core_id);
68 static void gpc_restore_imr_lpm(unsigned int core_id, unsigned int imr_idx)
70 	uint32_t reg = gpc_imr_offset[core_id] + imr_idx * 4;
71 	uint32_t val = gpc_saved_imrs[core_id + imr_idx * 4];
73 	gpc_imr_core_spin_lock(core_id);
77 	gpc_imr_core_spin_unlock(core_id);
156 static void imx_gpc_mask_irq0(uint32_t core_id, uint32_t mask)
158 	gpc_imr_core_spin_lock(core_id);
160 		mmio_setbits_32(gpc_imr_offset[core_id], 1);
162 		mmio_clrbits_32(gpc_imr_offset[core_id], 1);
166 	gpc_imr_core_spin_unlock(core_id);
178 void imx_gpc_set_a53_core_awake(uint32_t core_id)
180 	imx_gpc_mask_irq0(core_id, true);
217 void imx_set_cpu_pwr_off(unsigned int core_id)
222 	mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
223 			(1 << (core_id + 20)));
228 	mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
232 void imx_set_cpu_lpm(unsigned int core_id, bool pdn)
238 		mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
239 				(1 << (core_id + 20)) | COREx_IRQ_WUP(core_id));
241 		mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
244 		mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
245 				COREx_IRQ_WUP(core_id));
247 		mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);