Lines Matching defs:pwr_domain
175 struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id];
192 if (pwr_domain->need_sync) {
205 mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
208 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req);
211 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req)
234 if (pwr_domain->need_sync) {
236 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
239 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack))
250 if (pwr_domain->always_on) {
254 if (pwr_domain->need_sync) {
259 if (pwr_domain->need_sync) {
261 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
264 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack))
269 mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
289 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);
292 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req)