Lines Matching defs:domain_id
73 void vpu_sft_reset_assert(uint32_t domain_id)
79 switch (domain_id) {
97 void vpu_sft_reset_deassert(uint32_t domain_id)
103 switch (domain_id) {
121 void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on)
123 if (domain_id >= MAX_DOMAINS) {
127 struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id];
130 pu_domain_status |= (1 << domain_id);
132 if (domain_id == VPU_G1 || domain_id == VPU_G2 ||
133 domain_id == VPU_H1) {
134 vpu_sft_reset_assert(domain_id);
138 if (domain_id != HSIOMIX) {
151 if (domain_id == VPU_G1 || domain_id == VPU_G2 ||
152 domain_id == VPU_H1) {
153 vpu_sft_reset_deassert(domain_id);
158 if (domain_id == GPUMIX) {
191 if (domain_id == VPUMIX) {
201 if (domain_id == DISPMIX) {
219 if (domain_id == GPUMIX) {
237 pu_domain_status &= ~(1 << domain_id);
239 if (domain_id == OTG1 || domain_id == OTG2) {
244 if (domain_id == GPUMIX) {
271 if (domain_id == GPUMIX) {
294 if (domain_id != HSIOMIX) {