Lines Matching defs:dram_info

19 struct dram_info dram_info;
110 		if (dram_info.dram_type == DDRC_LPDDR4) {
121 	uint32_t pstate_num = dram_info.num_fsp;
128 		dram_info.rank_setting[i][0] = mmio_read_32(DDRC_DRAMTMG2(0) + offset);
129 		if (dram_info.dram_type != DDRC_LPDDR4) {
130 			dram_info.rank_setting[i][1] = mmio_read_32(DDRC_DRAMTMG9(0) + offset);
133 		dram_info.rank_setting[i][2] = mmio_read_32(DDRC_RANKCTL(0) + offset);
137 	dram_info.rank_setting[0][2] = mmio_read_32(DDRC_RANKCTL(0));
224 	dram_info.dram_type = ddrc_mstr & DDR_TYPE_MASK;
225 	dram_info.num_rank = ((ddrc_mstr >> 24) & ACTIVE_RANK_MASK) == 0x3 ?
231 	dram_info.boot_fsp = current_fsp;
232 	dram_info.current_fsp = current_fsp;
238 	get_mr_values(dram_info.mr_table);
240 	dram_info.timing_info = (struct dram_timing_info *)dram_timing_base;
244 		if (!dram_info.timing_info->fsp_table[i]) {
251 	dram_info.num_fsp = (i > MAX_FSP_NUM) ? MAX_FSP_NUM : i;
262 	if (dram_info.timing_info->fsp_table[idx] < 666) {
263 		dram_info.bypass_mode = true;
265 		dram_info.bypass_mode = false;
275 	if (dram_info.dram_type == DDRC_LPDDR4 && current_fsp != 0x0) {
278 		lpddr4_swffc(&dram_info, dev_fsp, 0x0);
283 		ddr4_swffc(&dram_info, 0x0);
308 		 SMC_RET4(handle, dram_info.timing_info->fsp_table[0],
311 		if (!dram_info.bypass_mode) {
312 			SMC_RET4(handle, dram_info.timing_info->fsp_table[1],
315 		SMC_RET4(handle, dram_info.timing_info->fsp_table[1],
318 		if (!dram_info.bypass_mode) {
319 			SMC_RET4(handle, dram_info.timing_info->fsp_table[2],
322 		SMC_RET4(handle, dram_info.timing_info->fsp_table[2],
325 		 SMC_RET4(handle, dram_info.timing_info->fsp_table[3],
341 		SMC_RET1(handle, dram_info.num_fsp);
372 		if (dram_info.dram_type == DDRC_LPDDR4) {
373 			lpddr4_swffc(&dram_info, dev_fsp, fsp_index);
376 			ddr4_swffc(&dram_info, fsp_index);
379 		dram_info.current_fsp = fsp_index;