Lines Matching defs:serdes

241  * PCIe RC serdes link width
371  * Bring up LCPLL channel 0 reference clock for PCIe serdes used in RC mode
442  * Bring up EXT CLK reference clock for PCIe serdes used in RC mode
484 	unsigned int serdes;
487 	for (serdes = 0; serdes < NUM_OF_PCIE_SERDES; serdes++) {
488 		val = pcie_ext_clk[pipemux_idx][serdes];
492 			      serdes * PCIE_CORE_PWR_OFFSET, val);
510 	unsigned int link_width, serdes, nr_serdes;
524 	for (serdes = 0; serdes < nr_serdes; serdes++) {
525 		mmio_write_32(pmi_base, serdes);
539 	int serdes;
548 	for (serdes = 0; serdes < nSerdes; serdes++) {
550 		mmio_write_32(pmi_base, serdes);
588 		/* to identify 2 lane serdes */
692 	unsigned int serdes;
697 	 * Each serdes has a x2 link width
699 	 * Use PAXB to patch the serdes for proper RX termination through the
703 	for (serdes = 0; serdes < nr_serdes; serdes++) {
705 		mmio_write_32(pmi_base, serdes);
730 		if (pcie_serdes_requires_patch(serdes)) {
776 			ERROR("PCIe serdes initialization failed for core %u\n",
784 			ERROR("PCIe GEN3 serdes initialization failed\n");