Lines Matching defs:core_idx
257 int pcie_core_needs_enable(unsigned int core_idx)
260 return paxb->core_needs_enable(core_idx);
265 static void pcie_set_default_tx_coeff(uint32_t core_idx, uint32_t link_width)
272 data = paxb_rc_cfg_read(core_idx, addr);
279 paxb_rc_cfg_write(core_idx, addr, data);
288 uint32_t core_idx;
290 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
291 if (!pcie_core_needs_enable(core_idx))
294 link_width = paxb->get_link_width(core_idx);
302 val = paxb_rc_cfg_read(core_idx, CFG_RC_LINK_CAP);
305 paxb_rc_cfg_write(core_idx, CFG_RC_LINK_CAP, val);
308 val = paxb_rc_cfg_read(core_idx, CFG_RC_LINK_CAP);
311 paxb_rc_cfg_write(core_idx, CFG_RC_LINK_CAP, val);
314 val = paxb_rc_cfg_read(core_idx, CFG_RC_LINK_STATUS_CTRL_2);
317 paxb_rc_cfg_write(core_idx, CFG_RC_LINK_STATUS_CTRL_2, val);
322 val = paxb_rc_cfg_read(core_idx, CFG_RC_REG_PHY_CTL_10);
324 paxb_rc_cfg_write(core_idx, CFG_RC_REG_PHY_CTL_10, val);
326 pcie_set_default_tx_coeff(core_idx, link_width);
332 static void paxb_perst_ctrl(unsigned int core_idx, bool assert)
334 uint32_t clk_ctrl = PAXB_OFFSET(core_idx) + PAXB_CLK_CTRL_OFFSET;
349 unsigned int core_idx;
352 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
353 if (!pcie_core_needs_enable(core_idx))
357 paxb_perst_ctrl(core_idx, true);
358 paxb_perst_ctrl(core_idx, false);
363 val = mmio_read_32(PAXB_OFFSET(core_idx) +
372 ERROR("PAXB core %u link is down\n", core_idx);
377 static void pcie_core_soft_reset(unsigned int core_idx)
379 uint32_t offset = core_idx * PCIE_CORE_PWR_OFFSET;
445 static int pcie_core_pwr_init(unsigned int core_idx)
448 uint32_t offset = core_idx * PCIE_CORE_PWR_OFFSET;
489 uint32_t core_idx;
501 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
502 if (!pcie_core_needs_enable(core_idx))
505 ret = pcie_core_pwr_init(core_idx);
507 ERROR("PCIe core %u power up failed\n", core_idx);
511 pcie_core_soft_reset(core_idx);
513 VERBOSE("PCIe core %u is powered up\n", core_idx);
519 void paxb_rc_cfg_write(unsigned int core_idx, unsigned int where,
522 mmio_write_32(PAXB_OFFSET(core_idx) + PAXB_CFG_IND_ADDR_OFFSET,
525 mmio_write_32(PAXB_OFFSET(core_idx) + PAXB_CFG_IND_DATA_OFFSET, val);
528 unsigned int paxb_rc_cfg_read(unsigned int core_idx, unsigned int where)
532 mmio_write_32(PAXB_OFFSET(core_idx) + PAXB_CFG_IND_ADDR_OFFSET,
535 val = mmio_read_32(PAXB_OFFSET(core_idx) + PAXB_CFG_IND_DATA_OFFSET);
542 uint32_t val, core_idx, mps;
544 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
545 if (!pcie_core_needs_enable(core_idx))
548 val = paxb_rc_cfg_read(core_idx, CFG_RC_DEVICE_CAP);
551 if (core_idx == 0 || core_idx == 1 ||
552 core_idx == 6 || core_idx == 7) {
556 paxb_rc_cfg_write(core_idx, CFG_RC_DEVICE_CAP, val);
562 uint32_t val, core_idx;
567 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
568 if (!pcie_core_needs_enable(core_idx))
573 (core_idx * PCIE_CORE_PWR_OFFSET), 1);
576 val = paxb_rc_cfg_read(core_idx, PCI_BRIDGE_CTRL_REG_OFFSET);
579 paxb_rc_cfg_write(core_idx, PCI_BRIDGE_CTRL_REG_OFFSET, val);
582 paxb_rc_cfg_write(core_idx, CFG_RC_DEV_ID, val);
585 paxb_rc_cfg_write(core_idx, CFG_RC_DEV_SUBID, val);
591 uint32_t val, core_idx;
599 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
600 if (!pcie_core_needs_enable(core_idx))
603 val = paxb_rc_cfg_read(core_idx, CFG_RC_TL_CTRL_0);
605 paxb_rc_cfg_write(core_idx, CFG_RC_TL_CTRL_0, val);
611 uint32_t val, core_idx;
615 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
616 if (!pcie_core_needs_enable(core_idx))
623 if (core_idx == 0 || core_idx == 1 ||
624 core_idx == 6 || core_idx == 7) {
629 val = paxb_rc_cfg_read(core_idx, CFG_RC_PDL_CTRL_4);
634 paxb_rc_cfg_write(core_idx, CFG_RC_PDL_CTRL_4, val);
636 val = paxb_rc_cfg_read(core_idx, CFG_RC_PDL_CTRL_5);
639 paxb_rc_cfg_write(core_idx, CFG_RC_PDL_CTRL_5, val);
646 paxb_rc_cfg_write(core_idx, CFG_RC_TL_FCIMM_NP_LIMIT,
649 paxb_rc_cfg_write(core_idx, CFG_RC_TL_FCIMM_P_LIMIT,
656 uint32_t val, core_idx;
658 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
659 if (!pcie_core_needs_enable(core_idx))
662 val = paxb_rc_cfg_read(core_idx, CFG_RC_CLKREQ_ENABLED);
664 paxb_rc_cfg_write(core_idx, CFG_RC_CLKREQ_ENABLED, val);
670 uint32_t val, core_idx;
672 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
673 if (!pcie_core_needs_enable(core_idx))
676 val = paxb_rc_cfg_read(core_idx, CFG_LINK_CAP_RC);
681 paxb_rc_cfg_write(core_idx, CFG_LINK_CAP_RC, val);
687 uint32_t val, core_idx;
689 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
690 if (!pcie_core_needs_enable(core_idx))
693 val = paxb_rc_cfg_read(core_idx, CFG_ROOT_CAP_RC);
698 paxb_rc_cfg_write(core_idx, CFG_ROOT_CAP_RC, val);
735 unsigned int core_idx;
737 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
738 if (!pcie_core_needs_enable(core_idx))
742 mmio_write_32(PAXB_OFFSET(core_idx) + PAXB_IARR2_LOWER_OFFSET,
744 mmio_setbits_32(PAXB_OFFSET(core_idx) +
752 unsigned int core_idx;
754 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
755 if (!pcie_core_needs_enable(core_idx))
759 mmio_write_32(PAXB_OFFSET(core_idx) +
767 unsigned int core_idx;
771 for (core_idx = 0; core_idx < paxb->num_cores; core_idx++) {
772 if (!pcie_core_needs_enable(core_idx))
775 offset = core_idx * PCIE_CORE_PWR_OFFSET;