Lines Matching defs:smmu
97 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
98 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift))
137 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
138 #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift))
306 static void arm_smmu_smr_cfg(struct arm_smmu_device *smmu, uint32_t index)
308 uint32_t idx = smmu->cfg[index].cbndx;
309 struct arm_smmu_smr *smr = &smmu->smr[index];
315 mmio_write_32((uintptr_t) (ARM_SMMU_GR0(smmu) +
319 static void arm_smmu_s2cr_cfg(struct arm_smmu_device *smmu, uint32_t index)
321 uint32_t idx = smmu->cfg[index].cbndx;
322 struct arm_smmu_s2cr *s2cr = &smmu->s2cr[index];
328 mmio_write_32((uintptr_t) (ARM_SMMU_GR0(smmu) +
332 static void smmu_set_pgtbl(struct arm_smmu_device *smmu,
401 struct arm_smmu_device *smmu = &iommu;
409 smmu->base = (uint8_t *) SMMU_BASE;
410 reg = mmio_read_32((uintptr_t) (ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_ID1));
411 smmu->pgshift = (reg & ID1_PAGESIZE) ? 16 : 12;
412 smmu->size = ARM_SMMU_RES_SIZE;
413 smmu->stream_ids = NULL;
417 smmu->stream_ids = &paxc_stream_ids[0];
418 smmu->stream_ids_mask = &paxc_stream_ids_mask[0];
419 smmu->streams = ARRAY_SIZE(paxc_stream_ids);
424 smmu->stream_ids = &crmu_stream_ids[0];
425 smmu->stream_ids_mask = &crmu_stream_ids_mask[0];
426 smmu->streams = ARRAY_SIZE(crmu_stream_ids);
435 if (smmu->streams > NUM_OF_SMRS) {
441 for (idx = 0; idx < smmu->streams; idx++) {
443 smmu->s2cr[idx].type = S2CR_TYPE_TRANS;
444 smmu->s2cr[idx].privcfg = S2CR_PRIVCFG_DEFAULT;
445 smmu->s2cr[idx].cbndx = context_bank_index;
446 smmu->cfg[idx].cbndx = context_bank_index;
447 smmu->cfg[idx].cbar = STG1_WITH_STG2_BYPASS << CBAR_TYPE_SHIFT;
448 arm_smmu_s2cr_cfg(smmu, idx);
451 smmu->smr[idx].mask = smmu->stream_ids_mask[idx];
452 smmu->smr[idx].id = smmu->stream_ids[idx];
453 smmu->smr[idx].valid = 1;
454 arm_smmu_smr_cfg(smmu, idx);
457 mmio_write_32((uintptr_t) (ARM_SMMU_GR1(smmu) +
458 ARM_SMMU_GR1_CBA2R(smmu->cfg[idx].cbndx)),
461 reg = smmu->cfg[idx].cbar;
465 mmio_write_32((uintptr_t) (ARM_SMMU_GR1(smmu) +
466 ARM_SMMU_GR1_CBAR(smmu->cfg[idx].cbndx)),
484 mmio_write_32((uintptr_t) (ARM_SMMU_CB_BASE(smmu) +
485 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) +
488 mmio_write_32((uintptr_t) (ARM_SMMU_CB_BASE(smmu) +
489 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) +
493 asid = smmu->cfg[idx].cbndx;
497 mmio_write_64((uintptr_t) (ARM_SMMU_CB_BASE(smmu) +
498 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) +
504 mmio_write_64((uintptr_t) (ARM_SMMU_CB_BASE(smmu) +
505 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) +
518 mmio_write_32((uintptr_t) (ARM_SMMU_CB_BASE(smmu) +
519 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) +
524 mmio_write_32((uintptr_t) (ARM_SMMU_CB_BASE(smmu) +
525 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) +
531 mmio_write_32((uintptr_t) (ARM_SMMU_CB_BASE(smmu) +
532 ARM_SMMU_CB(smmu, smmu->cfg[idx].cbndx) +
535 smmu_set_pgtbl(smmu, dom, (uint64_t *)pg_table_base);