Lines Matching defs:u2_phy
73 static void u2_phy_ext_fsm_power_on(struct u2_phy_ext_fsm *u2_phy)
75 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_ISO);
79 mmio_setbits_32(u2_phy->phy_ctrl_reg, u2_phy->phy_iddq);
83 mmio_clrbits_32(u2_phy->phy_ctrl_reg,
89 mmio_clrsetbits_32(u2_phy->phy_ctrl_reg,
95 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_CTRL_CORERDY);
99 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_BG_PWRDWNB);
103 mmio_setbits_32(u2_phy->pwr_ctrl_reg, u2_phy->pwr_onin);
104 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_LDO_PWRDWNB);
108 mmio_setbits_32(u2_phy->pwr_ctrl_reg, u2_phy->pwr_okin);
112 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_PLL_PWRDWNB);
116 mmio_clrbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_ISO);
119 mmio_clrbits_32(u2_phy->phy_ctrl_reg, u2_phy->phy_iddq);
123 mmio_setbits_32(u2_phy->pll_ctrl_reg, USB2_PLL_RESETB);
124 mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_RESETB);
131 struct u2_phy_ext_fsm u2_phy;
133 u2_phy.pll_ctrl_reg = base + USB3H_U2PLL_CTRL;
134 u2_phy.phy_ctrl_reg = base + USB3H_U2PHY_CTRL;
135 u2_phy.phy_iddq = USB3H_U2PHY_IDDQ;
136 u2_phy.pwr_ctrl_reg = base + USB3H_PWR_CTRL;
137 u2_phy.pwr_okin = USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWROKIN;
138 u2_phy.pwr_onin = USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWRONIN;
140 u2_phy_ext_fsm_power_on(&u2_phy);
187 struct u2_phy_ext_fsm u2_phy;
189 u2_phy.pll_ctrl_reg = base + DRDU3_U2PLL_CTRL;
190 u2_phy.phy_ctrl_reg = base + DRDU3_U2PHY_CTRL;
191 u2_phy.phy_iddq = DRDU3_U2PHY_IDDQ;
192 u2_phy.pwr_ctrl_reg = base + DRDU3_PWR_CTRL;
193 u2_phy.pwr_okin = DRDU3_U2PHY_DFE_SWITCH_PWROKIN;
194 u2_phy.pwr_onin = DRDU3_U2PHY_DFE_SWITCH_PWRONIN;
196 u2_phy_ext_fsm_power_on(&u2_phy);
245 struct u2_phy_ext_fsm u2_phy;
247 u2_phy.pll_ctrl_reg = base + DRDU2_U2PLL_CTRL;
248 u2_phy.phy_ctrl_reg = base + DRDU2_PHY_CTRL;
249 u2_phy.phy_iddq = DRDU2_U2IDDQ;
250 u2_phy.pwr_ctrl_reg = base + DRDU2_PWR_CTRL;
251 u2_phy.pwr_okin = DRDU2_U2PHY_DFE_SWITCH_PWROKIN_I;
252 u2_phy.pwr_onin = DRDU2_U2PHY_DFE_SWITCH_PWRONIN_I;
254 u2_phy_ext_fsm_power_on(&u2_phy);