Lines Matching defs:base

128 static int32_t usb3h_u2_phy_power_on(uint32_t base)
133 	u2_phy.pll_ctrl_reg = base + USB3H_U2PLL_CTRL;
134 	u2_phy.phy_ctrl_reg = base + USB3H_U2PHY_CTRL;
136 	u2_phy.pwr_ctrl_reg = base + USB3H_PWR_CTRL;
142 	status = pll_lock_check(base + USB3H_U2PLL_CTRL, USB3H_U2PLL_LOCK);
145 		mmio_clrbits_32(base + USB3H_U2PLL_CTRL,
147 		mmio_setbits_32(base + USB3H_U2PLL_CTRL, USB3H_U2PLL_RESETB);
148 		status = pll_lock_check(base + USB3H_U2PLL_CTRL,
152 			      base + USB3H_U2PLL_CTRL);
155 	mmio_clrsetbits_32(base + USB3H_U2PHY_CTRL,
161 static int32_t usb3h_u3_phy_power_on(uint32_t base)
166 	mmio_clrsetbits_32(base + USB3H_U3PHY_CTRL,
170 	mmio_clrbits_32(base + USB3H_U3PHY_PLL_CTRL,
172 	mmio_setbits_32(base + USB3H_U3PHY_PLL_CTRL, USB3H_U3PLL_SEQ_START);
173 	mmio_setbits_32(base + USB3H_U3PHY_PLL_CTRL, USB3H_U3PLL_RESETB);
178 	status = pll_lock_check(base + USB3H_U3PHY_PLL_CTRL,
184 static int32_t drdu3_u2_phy_power_on(uint32_t base)
189 	u2_phy.pll_ctrl_reg = base + DRDU3_U2PLL_CTRL;
190 	u2_phy.phy_ctrl_reg = base + DRDU3_U2PHY_CTRL;
192 	u2_phy.pwr_ctrl_reg = base + DRDU3_PWR_CTRL;
198 	status = pll_lock_check(base + DRDU3_U2PLL_CTRL, DRDU3_U2PLL_LOCK);
201 		mmio_clrbits_32(base + DRDU3_U2PLL_CTRL,
203 		mmio_setbits_32(base + DRDU3_U2PLL_CTRL, DRDU3_U2PLL_RESETB);
205 		status = pll_lock_check(base + DRDU3_U2PLL_CTRL,
209 			      base + DRDU3_U2PLL_CTRL);
212 	mmio_clrsetbits_32(base + DRDU3_U2PHY_CTRL,
219 static int32_t drdu3_u3_phy_power_on(uint32_t base)
224 	mmio_clrsetbits_32(base + DRDU3_U3PHY_CTRL,
228 	mmio_clrbits_32(base + DRDU3_U3PHY_PLL_CTRL,
230 	mmio_setbits_32(base + DRDU3_U3PHY_PLL_CTRL, DRDU3_U3PLL_SEQ_START);
231 	mmio_setbits_32(base + DRDU3_U3PHY_PLL_CTRL, DRDU3_U3PLL_RESETB);
236 	status = pll_lock_check(base + DRDU3_U3PHY_PLL_CTRL,
242 static int32_t drdu2_u2_phy_power_on(uint32_t base)
247 	u2_phy.pll_ctrl_reg = base + DRDU2_U2PLL_CTRL;
248 	u2_phy.phy_ctrl_reg = base + DRDU2_PHY_CTRL;
250 	u2_phy.pwr_ctrl_reg = base + DRDU2_PWR_CTRL;
256 	status = pll_lock_check(base + DRDU2_U2PLL_CTRL, DRDU2_U2PLL_LOCK);
259 		mmio_clrbits_32(base + DRDU2_U2PLL_CTRL,
261 		mmio_setbits_32(base + DRDU2_U2PLL_CTRL, DRDU2_U2PLL_RESETB);
263 		status = pll_lock_check(base + DRDU2_U2PLL_CTRL,
267 			      base + DRDU2_U2PLL_CTRL);
269 	mmio_clrsetbits_32(base + DRDU2_PHY_CTRL,